Fix small documentation errors

2020-12-28 10:50:10 -07:00
parent cb488b8137
commit fbb8ad3e61
3 changed files with 6 additions and 6 deletions
--- a/docs/Prototyping/General.rst
+++ b/docs/Prototyping/General.rst
@@ -15,7 +15,7 @@ To initialize the ``fpga-shells`` submodule repository, run the included initial
    ./scripts/init-fpga.sh

 Generating a Bitstream
------------------
+----------------------

 Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation.
 Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: