From fbb8ad3e61d664173361a1853ee7ef90246acab1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 28 Dec 2020 10:50:10 -0700 Subject: [PATCH] Fix small documentation errors --- docs/Prototyping/Arty.rst | 4 ++-- docs/Prototyping/General.rst | 2 +- docs/Prototyping/VCU118.rst | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/Prototyping/Arty.rst b/docs/Prototyping/Arty.rst index d01cc5c2..204eacec 100644 --- a/docs/Prototyping/Arty.rst +++ b/docs/Prototyping/Arty.rst @@ -1,8 +1,8 @@ Running a Design on Arty ======================== -Basic Design ------------- +Basic Arty Design +----------------- The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide `__. The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index a653f20a..0221b82b 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -15,7 +15,7 @@ To initialize the ``fpga-shells`` submodule repository, run the included initial ./scripts/init-fpga.sh Generating a Bitstream ------------------- +---------------------- Generating a bitstream for any FPGA target using Vivado is similar to building RTL for a software RTL simulation. Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream using Vivado: diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 9deb8739..c12e3714 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -1,8 +1,8 @@ Running a Design on VCU118 ========================== -Basic Design ------------- +Basic VCU118 Design +------------------- The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory. This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). @@ -52,4 +52,4 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. - See :ref:`Making a Bitstream` for information on the various make variables. + See :ref:`Generating a Bitstream` for information on the various make variables.