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Fix small documentation errors

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Abraham Gonzalez
2020-12-28 10:50:10 -07:00
parent cb488b8137
commit fbb8ad3e61
3 changed files with 6 additions and 6 deletions
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docs/Prototyping/Arty.rst
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@@ -1,8 +1,8 @@
Running a Design on Arty
========================
Basic Design
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Basic Arty Design
-----------------
The default Xilinx Arty 35T harness is setup to have JTAG available over the board's PMOD pins, and UART available over its FTDI serial USB adapter. The pin mappings for JTAG signals are identical to those described in the `SiFive Freedom E310 Arty 35T Getting Started Guide <https://static.dev.sifive.com/SiFive-E310-arty-gettingstarted-v1.0.6.pdf>`__.
The JTAG interface allows a user to connect to the core via OpenOCD, run bare-metal applications, and debug these applications with gdb. UART allows a user to communicate with the core over a USB connection and serial console running on a PC.