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Update comment for AbsoluteFreqHarnessClockInstantiator

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This commit is contained in:
Jerry Zhao
2023-05-14 21:48:38 -07:00
parent a207e37725
commit fa91426cf5
1 changed files with 2 additions and 2 deletions
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4
generators/chipyard/src/main/scala/harness/HarnessClocks.scala
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@@ -62,8 +62,8 @@ class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map(
// The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to
// provide the precise requested frequency.
// This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim
// It is useful for VCS/Xcelium-driven RTL simulations
// This ClockInstantiator cannot be synthesized or run in FireSim
// It is useful for RTL simulations
class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator {
def instantiateHarnessClocks(refClock: Clock, refClockFreqMHz: Double): Unit = {
// connect wires to clock source