wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #1431 from ucb-bar/bankedspad

Browse Source 
Support banked/partitioned scratchpads
This commit is contained in:
Jerry Zhao
2023-06-13 10:57:31 -07:00
committed by GitHub
parent d72158ec41 1e3d4aad46
commit fa6d77237e
4 changed files with 14 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C

12
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -74,13 +74,19 @@ class L1ScratchpadRocketConfig extends Config(
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
// DOC include start: mbusscratchpadrocket // DOC include start: mbusscratchpadrocket
class MbusScratchpadRocketConfig extends Config( class MbusScratchpadOnlyRocketConfig extends Config(
new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
// DOC include end: mbusscratchpadrocket // DOC include end: mbusscratchpadrocket
class SbusScratchpadRocketConfig extends Config(
new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class MulticlockRocketConfig extends Config( class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++

6
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -138,7 +138,7 @@ class WithFireSimConfigTweaks extends Config(
class WithMinimalFireSimHighPerfConfigTweaks extends Config( class WithMinimalFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++ new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ new freechips.rocketchip.subsystem.WithNoMemPort ++
new testchipip.WithBackingScratchpad ++ new testchipip.WithMbusScratchpad ++
new WithMinimalFireSimDesignTweaks new WithMinimalFireSimDesignTweaks
) )
@@ -148,7 +148,7 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config( class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
new WithFireSimHighPerfClocking ++ new WithFireSimHighPerfClocking ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
new testchipip.WithBackingScratchpad ++ // adds backing scratchpad for memory to replace FASED model new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
new testchipip.WithBlockDevice(true) ++ // add in block device new testchipip.WithBlockDevice(true) ++ // add in block device
new WithMinimalFireSimDesignTweaks new WithMinimalFireSimDesignTweaks
) )
@@ -329,7 +329,7 @@ class FireSim16LargeBoomConfig extends Config(
class FireSimNoMemPortConfig extends Config( class FireSimNoMemPortConfig extends Config(
new WithDefaultFireSimBridges ++ new WithDefaultFireSimBridges ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ new freechips.rocketchip.subsystem.WithNoMemPort ++
new testchipip.WithBackingScratchpad ++ new testchipip.WithMbusScratchpad ++
new WithFireSimConfigTweaks ++ new WithFireSimConfigTweaks ++
new chipyard.RocketConfig) new chipyard.RocketConfig)

2
generators/testchipip

Submodule generators/testchipip updated: a3e9c1ffea...35d7e1969d