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Increase default SerialTL width to 32 (#1040)

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This commit is contained in:
Jerry Zhao
2021-11-12 12:23:48 -08:00
committed by GitHub
parent 6a6fbe1a8d
commit f8d83dddf5
2 changed files with 3 additions and 0 deletions
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1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -42,6 +42,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithCustomBootPin ++ new chipyard.iobinders.WithCustomBootPin ++
new chipyard.iobinders.WithDividerOnlyClockGenerator ++ new chipyard.iobinders.WithDividerOnlyClockGenerator ++
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithUART ++ // add a UART

2
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -64,6 +64,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
// Non-frequency tweaks that are generally applied to all firesim configs // Non-frequency tweaks that are generally applied to all firesim configs
class WithFireSimDesignTweaks extends Config( class WithFireSimDesignTweaks extends Config(
// Optional: reduce the width of the Serial TL interface
new testchipip.WithSerialTLWidth(4) ++
// Required: Bake in the default FASED memory model // Required: Bake in the default FASED memory model
new WithDefaultMemModel ++ new WithDefaultMemModel ++
// Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset