From f8d83dddf56eea0d67283bfea6cd18e165a8eb44 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 Nov 2021 12:23:48 -0800 Subject: [PATCH] Increase default SerialTL width to 32 (#1040) --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 + generators/firechip/src/main/scala/TargetConfigs.scala | 2 ++ 2 files changed, 3 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 209bcf1f..ef44a500 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -42,6 +42,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithCustomBootPin ++ new chipyard.iobinders.WithDividerOnlyClockGenerator ++ + new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0c612cba..8ba903c6 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -64,6 +64,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") // Non-frequency tweaks that are generally applied to all firesim configs class WithFireSimDesignTweaks extends Config( + // Optional: reduce the width of the Serial TL interface + new testchipip.WithSerialTLWidth(4) ++ // Required: Bake in the default FASED memory model new WithDefaultMemModel ++ // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset