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Merge pull request #756 from ucb-bar/16-largeboom

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Add 16-core LargeBOOM config to firechip
This commit is contained in:
Albert Magyar
2021-01-13 15:36:51 -08:00
committed by GitHub
parent e9f64a8669 c481dc2ee8
commit f7a98f23bc
1 changed files with 11 additions and 0 deletions
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11
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -204,3 +204,14 @@ class FireSimMulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new FireSimRocketConfig) new FireSimRocketConfig)
//**********************************************************************************
// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
// - Requires MTModels and MCRams mixins as prefixes to the platform config
// - May require larger build instances or JVM memory footprints
//*********************************************************************************/
class FireSim16LargeBoomConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new boom.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)