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Remove redundant ChipTop reset synchronizer

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This commit is contained in:
Jerry Zhao
2020-10-28 15:34:14 -07:00
parent 93e57ef230
commit f4d70128c0
2 changed files with 2 additions and 4 deletions
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4
generators/chipyard/src/main/scala/Clocks.scala
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@@ -28,14 +28,12 @@ object GenerateReset {
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset",
abstractResetAsAsync = true) abstractResetAsAsync = true)
val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool())
chiptop.iocells ++= resetIOCell chiptop.iocells ++= resetIOCell
chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
reset_io := th.dutReset reset_io := th.dutReset
Nil Nil
}) })
reset_wire async_reset_wire
} }
} }

2
generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala
View File

@@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
* Instantiates a reset synchronizer on all clock-reset pairs in a clock group * Instantiates a reset synchronizer on all clock-reset pairs in a clock group
*/ */
class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
val node = ClockGroupIdentityNode() val node = ClockGroupAdapterNode()
lazy val module = new LazyRawModuleImp(this) { lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((oG, _), (iG, _)) => (node.out zip node.in).map { case ((oG, _), (iG, _)) =>
(oG.member.data zip iG.member.data).foreach { case (o, i) => (oG.member.data zip iG.member.data).foreach { case (o, i) =>