From f4d70128c007807ba7617f5c4fd47ebaf59c49c4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 28 Oct 2020 15:34:14 -0700 Subject: [PATCH] Remove redundant ChipTop reset synchronizer --- generators/chipyard/src/main/scala/Clocks.scala | 4 +--- .../chipyard/src/main/scala/clocking/ResetSynchronizer.scala | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala index 3c9e70cd..e4d48b59 100644 --- a/generators/chipyard/src/main/scala/Clocks.scala +++ b/generators/chipyard/src/main/scala/Clocks.scala @@ -28,14 +28,12 @@ object GenerateReset { val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true) - val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool()) - chiptop.iocells ++= resetIOCell chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => { reset_io := th.dutReset Nil }) - reset_wire + async_reset_wire } } diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala index 13a593c5..2ba8e855 100644 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync} * Instantiates a reset synchronizer on all clock-reset pairs in a clock group */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupIdentityNode() + val node = ClockGroupAdapterNode() lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) =>