Update multi-chip API for harnesses

2023-05-14 21:49:04 -07:00
parent fa91426cf5
commit f4739be632
6 changed files with 15 additions and 13 deletions
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -22,8 +22,6 @@ import chipyard.iobinders.{HasIOBinders}
 class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
  def dp = designParameters

-  require(dp(MultiChipNChips) == 0, "Arty100T harness does not support multi-chip")
-
  val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
  val harnessSysPLL = dp(PLLFactoryKey)
  val harnessSysPLLNode = harnessSysPLL()