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Update multi-chip API for harnesses

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This commit is contained in:
Jerry Zhao
2023-05-14 21:49:04 -07:00
parent fa91426cf5
commit f4739be632
6 changed files with 15 additions and 13 deletions
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2
fpga/src/main/scala/arty100t/Harness.scala
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@@ -22,8 +22,6 @@ import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters
require(dp(MultiChipNChips) == 0, "Arty100T harness does not support multi-chip")
val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
val harnessSysPLL = dp(PLLFactoryKey)
val harnessSysPLLNode = harnessSysPLL()

2
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -88,8 +88,6 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
}
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
require (p(MultiChipNChips) == 0)
val vc707Outer = _outer
val reset = IO(Input(Bool()))

2
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -91,8 +91,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
require(p(MultiChipNChips) == 0)
val vcu118Outer = _outer
val reset = IO(Input(Bool()))