update mem docs | add l1 scratchpad config

docs/Customization/Memory-Hierarchy.rst

@@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
     :language: scala
-    :start-after: DOC include start: scratchpadrocket
-    :end-before: DOC include end: scratchpadrocket
+    :start-after: DOC include start: l1scratchpadrocket
+    :end-before: DOC include end: l1scratchpadrocket
 
 
 This configuration fully removes the L2 cache and memory bus by setting the
@@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two.
 
     new freechips.rocketchip.subsystem.WithNMemoryChannels(2)
 
-
 In VCS and Verilator simulation, the DRAM is simulated using the
 ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each
 memory channel.
 
+Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
+and remove the off-chip link. This is done by adding a fragment like
+``testchipip.WithBackingScratchpad`` to your configuration and removing the
+memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+    :language: scala
+    :start-after: DOC include start: mbusscratchpadrocket
+    :end-before: DOC include end: mbusscratchpadrocket
+
 If you want a more realistic memory simulation, you can use FireSim, which
 can simulate the timing of DDR3 controllers. More documentation on FireSim
 memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_.

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -384,14 +384,35 @@ class LoopbackNICRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new freechips.rocketchip.system.BaseConfig)
 
-// DOC include start: scratchpadrocket
-class ScratchpadRocketConfig extends Config(
+// DOC include start: l1scratchpadrocket
+class L1ScratchpadSmallRocketConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++
   new chipyard.iobinders.WithTiedOffDebug ++
   new chipyard.iobinders.WithSimSerial ++
   new testchipip.WithTSI ++
-  new testchipip.WithBackingScratchpad ++              // add backing scratchpad
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 scratchpad
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: l1scratchpadrocket
+
+// DOC include start: mbusscratchpadrocket
+class MbusScratchpadRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new testchipip.WithBackingScratchpad ++                   // add mbus backing scratchpad
   new chipyard.config.WithBootROM ++
   new chipyard.config.WithUART ++
   new chipyard.config.WithL2TLBs(1024) ++
@@ -403,7 +424,7 @@ class ScratchpadRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new freechips.rocketchip.system.BaseConfig)
-// DOC include end: scratchpadrocket
+// DOC include end: mbusscratchpadrocket
 
 // DOC include start: RingSystemBusRocket
 class RingSystemBusRocketConfig extends Config(