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Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem

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This commit is contained in:
abejgonzalez
2020-11-23 16:58:34 -08:00
parent 8f6de22e72
commit f1fdab5bd3
3 changed files with 10 additions and 6 deletions
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7
fpga/src/main/scala/vcu118/Configs.scala
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@@ -39,11 +39,6 @@ class WithSystemModifications extends Config((site, here, up) => {
case SerialTLKey => None // remove serialized tl port case SerialTLKey => None // remove serialized tl port
}) })
class WithTLBackingMemory extends Config((site, here, up) => {
case ExtMem => None // disable AXI backing memory
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
// DOC include start: AbstractVCU118 and Rocket // DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config( class WithVCU118Tweaks extends Config(
new WithUART ++ new WithUART ++
@@ -53,7 +48,7 @@ class WithVCU118Tweaks extends Config(
new WithSPIIOPassthrough ++ new WithSPIIOPassthrough ++
new WithTLIOPassthrough ++ new WithTLIOPassthrough ++
new WithDefaultPeripherals ++ new WithDefaultPeripherals ++
new WithTLBackingMemory ++ // use TL backing memory new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++

5
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -181,6 +181,11 @@ class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusW
case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
}) })
class WithTLBackingMemory extends Config((site, here, up) => {
case ExtMem => None // disable AXI backing memory
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {

4
generators/chipyard/src/main/scala/System.scala
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@@ -51,6 +51,10 @@ case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
/** Adds a port to the system intended to master an TL DRAM controller. */ /** Adds a port to the system intended to master an TL DRAM controller. */
trait CanHaveMasterTLMemPort { this: BaseSubsystem => trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),
"Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.")
private val memPortParamsOpt = p(ExtTLMem) private val memPortParamsOpt = p(ExtTLMem)
private val portName = "tl_mem" private val portName = "tl_mem"
private val device = new MemoryDevice private val device = new MemoryDevice