Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -181,6 +181,11 @@ class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusW
   case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
 })
 
+class WithTLBackingMemory extends Config((site, here, up) => {
+  case ExtMem => None // disable AXI backing memory
+  case ExtTLMem => up(ExtMem, site) // enable TL backing memory
+})
+
 class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
 
 class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {

generators/chipyard/src/main/scala/System.scala

@@ -51,6 +51,10 @@ case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
 
 /** Adds a port to the system intended to master an TL DRAM controller. */
 trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+
+  require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),
+    "Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.")
+
   private val memPortParamsOpt = p(ExtTLMem)
   private val portName = "tl_mem"
   private val device = new MemoryDevice