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Dump per macro verilog (overridden by final verilog output)

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abejgonzalez
2023-10-16 16:08:53 -07:00
parent f5fe37c4bf
commit eef5efb93e
1 changed files with 2 additions and 0 deletions
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2
src/main/scala/barstools/macros/MacroCompiler.scala
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@@ -911,6 +911,7 @@ object MacroCompiler extends App {
.execute( .execute(
Array.empty, Array.empty,
Seq( Seq(
OutputFileAnnotation(params.get(Verilog).get),
RunFirrtlTransformAnnotation(new VerilogEmitter), RunFirrtlTransformAnnotation(new VerilogEmitter),
EmitCircuitAnnotation(classOf[VerilogEmitter]), EmitCircuitAnnotation(classOf[VerilogEmitter]),
FirrtlSourceAnnotation(circuit.serialize) FirrtlSourceAnnotation(circuit.serialize)
@@ -922,6 +923,7 @@ object MacroCompiler extends App {
.value .value
} }
.mkString("\n") .mkString("\n")
val verilogWriter = new FileWriter(new File(params.get(Verilog).get)) val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
verilogWriter.write(verilog) verilogWriter.write(verilog)
verilogWriter.close() verilogWriter.close()