From eef5efb93ee3df6296b8960605ba9ffa64a6d69e Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Mon, 16 Oct 2023 16:08:53 -0700
Subject: [PATCH] Dump per macro verilog (overridden by final verilog output)

---
 src/main/scala/barstools/macros/MacroCompiler.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/main/scala/barstools/macros/MacroCompiler.scala b/src/main/scala/barstools/macros/MacroCompiler.scala
index baed8411..6bcd06c5 100644
--- a/src/main/scala/barstools/macros/MacroCompiler.scala
+++ b/src/main/scala/barstools/macros/MacroCompiler.scala
@@ -911,6 +911,7 @@ object MacroCompiler extends App {
               .execute(
                 Array.empty,
                 Seq(
+                  OutputFileAnnotation(params.get(Verilog).get),
                   RunFirrtlTransformAnnotation(new VerilogEmitter),
                   EmitCircuitAnnotation(classOf[VerilogEmitter]),
                   FirrtlSourceAnnotation(circuit.serialize)
@@ -922,6 +923,7 @@ object MacroCompiler extends App {
               .value
           }
           .mkString("\n")
+
         val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
         verilogWriter.write(verilog)
         verilogWriter.close()