changes for new rocket-chip

This commit is contained in:
Donggyu Kim
2018-01-15 12:58:46 -08:00
committed by Howard Mao
parent 269660bbfe
commit ed13397967
5 changed files with 17 additions and 4 deletions

View File

@@ -3,8 +3,8 @@ package example
import chisel3._ import chisel3._
import freechips.rocketchip.config.{Parameters, Config} import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.tile.XLen import freechips.rocketchip.tile.XLen
import testchipip._ import testchipip._
@@ -13,9 +13,15 @@ class WithBootROM extends Config((site, here, up) => {
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
}) })
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
class WithExampleTop extends Config((site, here, up) => { class WithExampleTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new ExampleTop()(p)).module) Module(LazyModule(new ExampleTop()(p)).module)
}
}) })
class WithPWM extends Config((site, here, up) => { class WithPWM extends Config((site, here, up) => {

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@@ -13,7 +13,10 @@ class TestHarness(implicit val p: Parameters) extends Module {
}) })
val dut = p(BuildTop)(clock, reset.toBool, p) val dut = p(BuildTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem() dut.connectSimAXIMem()
dut.dontTouchPorts()
dut.tieOffInterrupts()
io.success := dut.connectSimSerial() io.success := dut.connectSimSerial()
} }

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@@ -4,12 +4,14 @@ import chisel3._
import freechips.rocketchip.coreplex._ import freechips.rocketchip.coreplex._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
import testchipip._ import testchipip._
class ExampleTop(implicit p: Parameters) extends RocketCoreplex class ExampleTop(implicit p: Parameters) extends RocketCoreplex
with HasMasterAXI4MemPort with HasMasterAXI4MemPort
with HasPeripheryBootROM with HasPeripheryBootROM
with HasSystemErrorSlave with HasSystemErrorSlave
with HasSyncExtInterrupts
with HasNoDebug with HasNoDebug
with HasPeripherySerial { with HasPeripherySerial {
override lazy val module = new ExampleTopModule(this) override lazy val module = new ExampleTopModule(this)
@@ -19,8 +21,10 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
with HasRTCModuleImp with HasRTCModuleImp
with HasMasterAXI4MemPortModuleImp with HasMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp with HasPeripheryBootROMModuleImp
with HasExtInterruptsModuleImp
with HasNoDebugModuleImp with HasNoDebugModuleImp
with HasPeripherySerialModuleImp with HasPeripherySerialModuleImp
with DontTouch
class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
with HasPeripheryPWM { with HasPeripheryPWM {