diff --git a/rocket-chip b/rocket-chip
index 86a19532..8799508b 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 86a19532871b118ff2de9dcabb0938158cd0e48b
+Subproject commit 8799508b1f374b7fe8086c46228f08fd2095d0df
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index d2794ce2..f7302e8f 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -3,8 +3,8 @@ package example
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
 import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
+import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.tile.XLen
 import testchipip._
 
@@ -13,9 +13,15 @@ class WithBootROM extends Config((site, here, up) => {
     contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
 })
 
+object ConfigValName {
+  implicit val valName = ValName("TestHarness")
+}
+import ConfigValName._
+
 class WithExampleTop extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
     Module(LazyModule(new ExampleTop()(p)).module)
+  }
 })
 
 class WithPWM extends Config((site, here, up) => {
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index 522f4993..ecda7047 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -13,7 +13,10 @@ class TestHarness(implicit val p: Parameters) extends Module {
   })
 
   val dut = p(BuildTop)(clock, reset.toBool, p)
+  dut.debug := DontCare
   dut.connectSimAXIMem()
+  dut.dontTouchPorts()
+  dut.tieOffInterrupts()
   io.success := dut.connectSimSerial()
 }
 
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index bacc5a02..b0f9ba83 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -4,12 +4,14 @@ import chisel3._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.util.DontTouch
 import testchipip._
 
 class ExampleTop(implicit p: Parameters) extends RocketCoreplex
     with HasMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasSystemErrorSlave
+    with HasSyncExtInterrupts
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)
@@ -19,8 +21,10 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
     with HasRTCModuleImp
     with HasMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
+    with HasExtInterruptsModuleImp
     with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
+    with DontTouch
 
 class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
     with HasPeripheryPWM {
diff --git a/testchipip b/testchipip
index 3fe88068..749311fd 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 3fe880689021006fb24e928dae3b117bf4b049fe
+Subproject commit 749311fd91edeb253f4e486240e61949c234afa3