changes for new rocket-chip

This commit is contained in:
Donggyu Kim
2018-01-15 12:58:46 -08:00
committed by Howard Mao
parent 269660bbfe
commit ed13397967
5 changed files with 17 additions and 4 deletions

View File

@@ -3,8 +3,8 @@ package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.tile.XLen
import testchipip._
@@ -13,9 +13,15 @@ class WithBootROM extends Config((site, here, up) => {
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
class WithExampleTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new ExampleTop()(p)).module)
}
})
class WithPWM extends Config((site, here, up) => {