Have Verilator build with unused simulation files
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@@ -46,9 +46,21 @@ debug: $(sim_debug)
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#########################################################################################
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# simulaton requirements
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#########################################################################################
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# past emulator.cc and verilator.h, the other files may not be used in the simulation but
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# are needed for emulator.cc to compile
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SIM_FILE_REQS += \
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$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h
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$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
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$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
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$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
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# copy files and add -FI for *.h files in *.f
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$(sim_files): $(SIM_FILE_REQS)
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