From eb85415783f25f0cf51b624b4cf1f6f8ba6a20c4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 6 May 2021 15:09:40 -0700 Subject: [PATCH] Have Verilator build with unused simulation files --- sims/verilator/Makefile | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9c8f3fa6..00c0f1bb 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -46,9 +46,21 @@ debug: $(sim_debug) ######################################################################################### # simulaton requirements ######################################################################################### +# past emulator.cc and verilator.h, the other files may not be used in the simulation but +# are needed for emulator.cc to compile SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h + $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ + $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ + $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS)