wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/main' into clusters

Browse Source
This commit is contained in:
Jerry Zhao
2023-12-15 15:53:35 -08:00
parent c5921ddef2 f882280290
commit e7f10348b0
80 changed files with 3722 additions and 2870 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {

4
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
View File

@@ -13,7 +13,7 @@ import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
extends Port[TSIHostWidgetIO]
class WithTSITLIOPassthrough extends OverrideIOBinder({
@@ -25,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
require(system.tsiSerial.size == 1)
val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
io_tsi_serial_pins_temp <> system.tsiSerial.head
(Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
(Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
}
})