Make no tlmonitor the default config, add explicit example on how to add tlmonitors

docs/Simulation/Software-RTL-Simulation.rst

@@ -223,3 +223,29 @@ The ``VERILATOR_THREADS=<num>`` option enables the compiled Verilator simulator
 On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``.
 By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator-<name> <simulator-args>``.
 Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation).
+
+
+When the SoC Hangs Due to Bad Tilelink Messages
+-----------------------------------------------
+
+There are many cases when your custom module interfaces with Tilelink (e.g., when you write a custom accelerator).
+Wrong interfaces with Tilelink can cause the SoC to hang and can be tricky to debug.
+To help deal with these situations, you can add hardware modules called Tilelink monitors into
+your SoC that will fire assertions when wrong Tilelink messages are sent.
+
+You can simply add these modules into your SoC by adding the below line into your config.
+
+.. code-block:: scala
+
+  new chipyard.config.WithTLMonitors ++
+
+
+For instance:
+
+.. code-block:: scala
+
+  class TLMonitorRocketConfig extends Config(
+    new chipyard.config.WithTLMonitors ++
+    new chipyard.RocketConfig)
+
+One caveat is that adding these modules can slow down your RTL simulation by around 2x.

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -81,6 +81,7 @@ class AbstractConfig extends Config(
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemClockIO ++                     // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++           // Don't add TL Monitors in the default configuration
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++      // Default 1 memory channels
   new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
   new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -96,3 +96,7 @@ class ClusteredRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithCluster(1) ++
   new freechips.rocketchip.subsystem.WithCluster(0) ++
   new chipyard.config.AbstractConfig)
+
+class TLMonitorRocketConfig extends Config(
+  new chipyard.config.WithTLMonitors ++
+  new chipyard.RocketConfig)

generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala

@@ -2,7 +2,7 @@ package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy.{DTSTimebase}
+import freechips.rocketchip.diplomacy.{DTSTimebase, MonitorsEnabled}
 import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
@@ -31,3 +31,7 @@ class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = In
 class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
   case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
 })
+
+class WithTLMonitors extends Config((site, here, up) => {
+  case MonitorsEnabled => true
+})