This is mess clean it up
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chick
@@ -1,181 +0,0 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.clkgen
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import chisel3._
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import firrtl._
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import org.scalatest.{FlatSpec, Matchers}
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import chisel3.experimental._
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import chisel3.iotesters._
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import chisel3.util.HasBlackBoxInline
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import barstools.tapeout.transforms.pads.TopModule
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// Purely to see that clk src tagging works with BBs
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class FakeBBClk extends BlackBox with HasBlackBoxInline with IsClkModule {
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val io = IO(new Bundle {
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val inClk = Input(Clock())
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val outClk = Output(Vec(3, Clock()))
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})
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annotateClkPort(io.inClk, Sink())
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val generatedClks = io.outClk.map { case elt =>
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val id = getIOName(elt)
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val srcId = getIOName(io.inClk)
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annotateClkPort(elt.asInstanceOf[Element])
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GeneratedClk(id, Seq(srcId), Seq(0, 1, 2))
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}.toSeq
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annotateDerivedClks(ClkDiv, generatedClks)
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// Generates a "FakeBB.v" file with the following Verilog module
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setInline("FakeBBClk.v",
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s"""
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|module FakeBBClk(
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| input inClk,
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| output outClk_0,
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| output outClk_1,
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| output outClk_2
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|);
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| always @* begin
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| outClk_0 = inClk;
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| outClk_1 = inClk;
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| outClk_2 = inClk;
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| end
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|endmodule
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""".stripMargin)
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}
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class ModWithNestedClkIO(numPhases: Int) extends Bundle {
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val inClk = Input(Clock())
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val bbOutClk = Output(Vec(3, Clock()))
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val clkDivOut = Output(Vec(numPhases, Clock()))
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}
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class TestModWithNestedClkIO(numPhases: Int) extends Bundle {
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val bbOutClk = Output(Vec(3, Bool()))
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val clkDivOut = Output(Vec(numPhases, Bool()))
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}
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class ModWithNestedClk(divBy: Int, phases: Seq[Int], syncReset: Boolean) extends Module {
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val io = IO(new ModWithNestedClkIO(phases.length))
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val bb = Module(new FakeBBClk)
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bb.io.inClk := io.inClk
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io.bbOutClk := bb.io.outClk
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val clkDiv = Module(new SEClkDivider(divBy, phases, syncReset = syncReset))
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clkDiv.io.reset := reset
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clkDiv.io.inClk := io.inClk
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phases.zipWithIndex.foreach { case (phase, idx) => io.clkDivOut(idx) := clkDiv.io.outClks(phase) }
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}
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class TopModuleWithClks(val divBy: Int, val phases: Seq[Int]) extends TopModule(usePads = false) {
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val io = IO(new Bundle {
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val gen1 = new TestModWithNestedClkIO(phases.length)
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val gen2 = new TestModWithNestedClkIO(phases.length)
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val gen3 = new TestModWithNestedClkIO(phases.length)
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val fakeClk1 = Input(Clock())
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val fakeClk2 = Input(Clock())
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})
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// TODO: Don't have to type Some
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annotateClkPort(clock,
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id = "clock", // not in io bundle
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sink = Sink(Some(ClkSrc(period = 5.0, async = Seq(getIOName(io.fakeClk1)))))
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)
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annotateClkPort(io.fakeClk1, Sink(Some(ClkSrc(period = 4.0))))
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annotateClkPort(io.fakeClk2, Sink(Some(ClkSrc(period = 3.0))))
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// Most complicated: test chain of clock generators
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val gen1 = Module(new ModWithNestedClk(divBy, phases, syncReset = true))
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io.gen1.bbOutClk := Vec(gen1.io.bbOutClk.map(x => x.asUInt))
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io.gen1.clkDivOut := Vec(gen1.io.clkDivOut.map(x => x.asUInt))
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gen1.io.inClk := clock
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// ClkDiv on generated clk -> reset occurs before first input clk edge
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val gen2 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
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io.gen2.bbOutClk := Vec(gen2.io.bbOutClk.map(x => x.asUInt))
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io.gen2.clkDivOut := Vec(gen2.io.clkDivOut.map(x => x.asUInt))
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gen2.io.inClk := gen1.io.clkDivOut.last
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val gen3 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
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io.gen3.bbOutClk := Vec(gen3.io.bbOutClk.map(x => x.asUInt))
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io.gen3.clkDivOut := Vec(gen3.io.clkDivOut.map(x => x.asUInt))
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gen3.io.inClk := gen1.io.clkDivOut.last
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}
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class TopModuleWithClksTester(c: TopModuleWithClks) extends PeekPokeTester(c) {
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val maxT = c.divBy * c.divBy * 4
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val numSubClkOutputs = c.io.gen1.clkDivOut.length
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val gen1Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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val gen2Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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val gen3Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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reset(10)
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for (t <- 0 until maxT) {
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for (k <- 0 until numSubClkOutputs) {
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gen1Out(k) += peek(c.io.gen1.clkDivOut(k)).intValue
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gen2Out(k) += peek(c.io.gen2.clkDivOut(k)).intValue
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gen3Out(k) += peek(c.io.gen3.clkDivOut(k)).intValue
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}
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step(1)
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}
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val clkCounts = (0 until maxT)
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val clkCountsModDiv = clkCounts.map(_ % c.divBy)
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for (k <- 0 until numSubClkOutputs) {
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val expected = clkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0)
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expect(gen1Out(k) == expected, s"gen1Out($k) incorrect!")
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println(s"gen1Out($k): \t${gen1Out(k).mkString("")}")
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}
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val gen1ClkCounts = (0 until maxT/c.divBy).map(i => Seq.fill(c.divBy)(i)).flatten
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val gen1ClkCountsModDiv = gen1ClkCounts.map(_ % c.divBy)
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for (k <- 0 until numSubClkOutputs) {
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// Handle initial transient
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val fillVal = if (c.phases.last == c.divBy - 1 && k == numSubClkOutputs - 1) 1 else 0
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val expected = Seq.fill(c.phases.last)(fillVal) ++
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gen1ClkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0).dropRight(c.phases.last)
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expect(gen2Out(k) == expected, s"gen1Out($k) incorrect!")
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println(s"gen2Out($k): \t${gen2Out(k).mkString("")}")
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println(s"expected: \t${expected.mkString("")}")
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}
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expect(gen2Out == gen3Out, "gen2Out should equal gen3Out")
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}
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class ClkGenSpec extends FlatSpec with Matchers {
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def readOutputFile(dir: String, f: String): String =
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scala.io.Source.fromFile(Seq(dir, f).mkString("/")).getLines.mkString("\n")
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def readResource(resource: String): String = {
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val stream = getClass.getResourceAsStream(resource)
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scala.io.Source.fromInputStream(stream).mkString
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}
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def checkOutputs(dir: String) = {
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}
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behavior of "top module with clk gens"
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it should "pass simple testbench" in {
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val optionsManager = new TesterOptionsManager {
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firrtlOptions = firrtlOptions.copy(
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compilerName = "verilog"
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/*annotations = List(passes.clocklist.ClockListAnnotation(
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s"-c:TopModuleWithClks:-m:TopModuleWithClks:-o:test.clk"
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)),
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customTransforms = Seq(new passes.clocklist.ClockListTransform())*/
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)
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testerOptions = testerOptions.copy(isVerbose = false, backendName = "verilator", displayBase = 10)
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commonOptions = commonOptions.copy(targetDirName = "test_run_dir/ClkTB")
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}
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// WARNING: TB requires that phase divBy - 1 should be at the end of the Seq to be OK during initial transient
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iotesters.Driver.execute(() => new TopModuleWithClks(4, Seq(0, 1, 3)), optionsManager) { c =>
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val dir = optionsManager.commonOptions.targetDirName
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checkOutputs(dir)
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new TopModuleWithClksTester(c)
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} should be (true)
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}
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}
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