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Fix FIFO-fixing

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Fragmenter infront of FIFO-fixer needs to track way too many source-Ids
This commit is contained in:
Jerry Zhao
2023-07-19 18:41:49 -07:00
parent 47faa5a605
commit dfb991770a
2 changed files with 5 additions and 6 deletions
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6
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_bus.get
clockSelector.tlNode := system.prci_ctrl_bus.get
pllCtrl.tlNode := system.prci_ctrl_bus.get
clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get
clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get
pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode

5
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
View File

@@ -42,7 +42,6 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
:= TLBuffer()
:= _)
})
@@ -87,13 +86,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
}
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
clock_gater.tlNode := prci_ctrl_bus.get
clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
clock_gater
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
reset_setter.tlNode := prci_ctrl_bus.get
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
reset_setter
} }