Write flop tests using generator
This commit is contained in:
Edward Wang
@@ -1,333 +1,334 @@
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//~ package barstools.tapeout.transforms.macros
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package barstools.macros
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//~ import java.io.File
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// Use this trait for tests that invoke the memory compiler without lib.
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trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
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this: MacroCompilerSpec with HasSRAMGenerator =>
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//~ class Synflops2048x16_mrw extends MacroCompilerSpec {
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// If there isn't a lib, then the "lib" will become a FIRRTL "mem", which
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//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
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// in turn becomes synthesized flops.
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//~ val v = new File(testDir, "syn_flops_2048x16_mrw.v")
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// Therefore, make "lib" width/depth equal to the mem.
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//~ val output =
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override lazy val libDepth = memDepth
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//~ """
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override lazy val libWidth = memWidth
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//~ circuit name_of_sram_module :
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// Do the same for port names.
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//~ module name_of_sram_module :
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override lazy val libPortPrefix = memPortPrefix
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//~ input clock : Clock
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//~ input RW0A : UInt<11>
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//~ input RW0I : UInt<16>
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//~ output RW0O : UInt<16>
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//~ input RW0E : UInt<1>
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//~ input RW0W : UInt<1>
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//~ input RW0M : UInt<2>
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//~ mem ram :
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// If there is no lib, don't generate a body.
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//~ data-type => UInt<8>[2]
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override def generateBody = ""
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//~ depth => 2048
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}
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//~ read-latency => 0
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//~ write-latency => 1
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//~ reader => R_0
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//~ writer => W_0
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//~ read-under-write => undefined
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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//~ ram.R_0.clk <= clock
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//~ ram.R_0.addr <= R_0_addr_reg
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//~ ram.R_0.en <= RW0E
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//~ RW0O <= cat(ram.R_0.data[1], ram.R_0.data[0])
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//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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//~ ram.W_0.clk <= clock
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//~ ram.W_0.addr <= RW0A
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//~ ram.W_0.en <= and(RW0E, RW0W)
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//~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
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//~ ram.W_0.data[1] <= bits(RW0I, 15, 8)
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//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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//~ """
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//~ compile(mem, None, v, true)
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//~ execute(Some(mem), None, true, output)
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//~ }
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//~ class Synflops2048x8_r_mw extends MacroCompilerSpec {
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// Test flop synthesis of the memory compiler.
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//~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
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//~ val v = new File(testDir, "syn_flops_2048x8_r_mw.v")
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//~ val output =
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//~ """
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//~ circuit name_of_sram_module :
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//~ module name_of_sram_module :
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//~ input clock : Clock
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//~ input W0A : UInt<11>
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//~ input W0I : UInt<8>
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//~ input W0E : UInt<1>
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//~ input W0M : UInt<1>
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//~ input clock : Clock
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//~ input R0A : UInt<11>
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//~ output R0O : UInt<8>
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//~ mem ram :
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trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {
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//~ data-type => UInt<8>[1]
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this: MacroCompilerSpec with HasSRAMGenerator =>
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//~ depth => 2048
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def generateFlops: String = {
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//~ read-latency => 0
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s"""
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//~ write-latency => 1
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mem ram :
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//~ reader => R_0
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data-type => UInt<${libWidth}>
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//~ writer => W_0
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depth => ${libDepth}
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//~ read-under-write => undefined
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read-latency => 1
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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write-latency => 1
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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readwriter => RW_0
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//~ ram.R_0.clk <= clock
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read-under-write => undefined
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//~ ram.R_0.addr <= R_0_addr_reg
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ram.RW_0.clk <= ${libPortPrefix}_clk
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//~ ram.R_0.en <= UInt<1>("h1")
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ram.RW_0.addr <= ${libPortPrefix}_addr
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//~ R0O <= ram.R_0.data[0]
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ram.RW_0.en <= UInt<1>("h1")
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//~ R_0_addr_reg <= mux(UInt<1>("h1"), R0A, R_0_addr_reg)
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ram.RW_0.wmode <= ${libPortPrefix}_write_en
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//~ ram.W_0.clk <= clock
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${libPortPrefix}_dout <= ram.RW_0.rdata
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//~ ram.W_0.addr <= W0A
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ram.RW_0.wdata <= ${libPortPrefix}_din
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//~ ram.W_0.en <= W0E
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ram.RW_0.wmask <= UInt<1>("h1")
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//~ ram.W_0.data[0] <= bits(W0I, 7, 0)
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"""
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//~ ram.W_0.mask[0] <= bits(W0M, 0, 0)
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}
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//~ """
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//~ compile(mem, None, v, true)
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//~ execute(Some(mem), None, true, output)
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//~ }
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//~ class Synflops2048x10_rw extends MacroCompilerSpec {
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// If there is no lib, put the flops definition into the body.
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//~ val mem = new File(macroDir, "lib-2048x10-rw.json")
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abstract override def generateBody = {
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//~ val v = new File(testDir, "syn_flops_2048x10_rw.v")
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if (this.isInstanceOf[HasNoLibTestGenerator]) generateFlops else super.generateBody
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//~ val output =
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}
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//~ """
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//~ circuit vendor_sram :
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//~ module vendor_sram :
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//~ input clock : Clock
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//~ input RW0A : UInt<11>
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//~ input RW0I : UInt<10>
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//~ output RW0O : UInt<10>
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//~ input RW0E : UInt<1>
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//~ input RW0W : UInt<1>
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//~ mem ram :
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// If there is no lib, don't generate a footer, since the flops definition
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//~ data-type => UInt<10>
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// will be in the body.
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//~ depth => 2048
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override def generateFooter = {
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//~ read-latency => 0
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if (this.isInstanceOf[HasNoLibTestGenerator]) "" else
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//~ write-latency => 1
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s"""
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//~ reader => R_0
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module ${lib_name} :
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//~ writer => W_0
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${generateFooterPorts}
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//~ read-under-write => undefined
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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//~ ram.R_0.clk <= clock
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//~ ram.R_0.addr <= R_0_addr_reg
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//~ ram.R_0.en <= RW0E
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//~ RW0O <= ram.R_0.data
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//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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//~ ram.W_0.clk <= clock
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//~ ram.W_0.addr <= RW0A
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//~ ram.W_0.en <= and(RW0E, RW0W)
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//~ ram.W_0.data <= RW0I
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//~ ram.W_0.mask <= UInt<1>("h1")
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//~ """
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//~ compile(mem, None, v, true)
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//~ execute(Some(mem), None, true, output)
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//~ }
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//~ class Synflops2048x8_mrw_re extends MacroCompilerSpec {
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${generateFlops}
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//~ val mem = new File(macroDir, "lib-2048x8-mrw-re.json")
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"""
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//~ val v = new File(testDir, "syn_flops_2048x8_mrw_re.v")
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}
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//~ val output =
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//~ """
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//~ circuit vendor_sram :
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//~ module vendor_sram :
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//~ input clock : Clock
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//~ input RW0A : UInt<11>
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//~ input RW0I : UInt<8>
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//~ output RW0O : UInt<8>
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//~ input RW0E : UInt<1>
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//~ input RW0R : UInt<1>
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//~ input RW0W : UInt<1>
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//~ input RW0M : UInt<1>
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//~ mem ram :
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}
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//~ data-type => UInt<8>[1]
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//~ depth => 2048
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//~ read-latency => 0
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//~ write-latency => 1
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//~ reader => R_0
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//~ writer => W_0
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//~ read-under-write => undefined
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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//~ ram.R_0.clk <= clock
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//~ ram.R_0.addr <= R_0_addr_reg
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//~ ram.R_0.en <= and(RW0E, not(RW0R))
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//~ RW0O <= ram.R_0.data[0]
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//~ R_0_addr_reg <= mux(and(RW0E, not(RW0R)), RW0A, R_0_addr_reg)
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//~ ram.W_0.clk <= clock
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//~ ram.W_0.addr <= RW0A
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//~ ram.W_0.en <= and(RW0E, RW0W)
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//~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
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//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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//~ """
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//~ compile(mem, None, v, true)
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//~ execute(Some(mem), None, true, output)
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//~ }
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//~ class Synflops2048x16_n28 extends MacroCompilerSpec {
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class Synflops2048x8_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
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//~ val mem = new File(macroDir, "lib-2048x16-n28.json")
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override lazy val memDepth = 2048
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//~ val v = new File(testDir, "syn_flops_2048x16_n28.v")
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override lazy val memWidth = 8
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//~ val output =
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//~ """
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//~ circuit vendor_sram_4 :
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//~ module vendor_sram_16 :
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//~ input clock : Clock
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//~ input RW0A : UInt<11>
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//~ input RW0I : UInt<16>
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//~ output RW0O : UInt<16>
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//~ input RW0E : UInt<1>
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//~ input RW0W : UInt<1>
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//~ input RW0M : UInt<16>
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//~ mem ram :
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compileExecuteAndTest(mem, None, v, output, true)
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//~ data-type => UInt<1>[16]
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}
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//~ depth => 2048
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//~ read-latency => 0
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//~ write-latency => 1
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//~ reader => R_0
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//~ writer => W_0
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//~ read-under-write => undefined
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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//~ ram.R_0.clk <= clock
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//~ ram.R_0.addr <= R_0_addr_reg
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//~ ram.R_0.en <= RW0E
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//~ RW0O <= cat(ram.R_0.data[15], cat(ram.R_0.data[14], cat(ram.R_0.data[13], cat(ram.R_0.data[12], cat(ram.R_0.data[11], cat(ram.R_0.data[10], cat(ram.R_0.data[9], cat(ram.R_0.data[8], cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))))))))))
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//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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//~ ram.W_0.clk <= clock
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//~ ram.W_0.addr <= RW0A
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//~ ram.W_0.en <= and(RW0E, RW0W)
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//~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
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//~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
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//~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
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//~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
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//~ ram.W_0.data[4] <= bits(RW0I, 4, 4)
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//~ ram.W_0.data[5] <= bits(RW0I, 5, 5)
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//~ ram.W_0.data[6] <= bits(RW0I, 6, 6)
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//~ ram.W_0.data[7] <= bits(RW0I, 7, 7)
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//~ ram.W_0.data[8] <= bits(RW0I, 8, 8)
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//~ ram.W_0.data[9] <= bits(RW0I, 9, 9)
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//~ ram.W_0.data[10] <= bits(RW0I, 10, 10)
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//~ ram.W_0.data[11] <= bits(RW0I, 11, 11)
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//~ ram.W_0.data[12] <= bits(RW0I, 12, 12)
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//~ ram.W_0.data[13] <= bits(RW0I, 13, 13)
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//~ ram.W_0.data[14] <= bits(RW0I, 14, 14)
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//~ ram.W_0.data[15] <= bits(RW0I, 15, 15)
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//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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//~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
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//~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
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//~ ram.W_0.mask[4] <= bits(RW0M, 4, 4)
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//~ ram.W_0.mask[5] <= bits(RW0M, 5, 5)
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//~ ram.W_0.mask[6] <= bits(RW0M, 6, 6)
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//~ ram.W_0.mask[7] <= bits(RW0M, 7, 7)
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//~ ram.W_0.mask[8] <= bits(RW0M, 8, 8)
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//~ ram.W_0.mask[9] <= bits(RW0M, 9, 9)
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//~ ram.W_0.mask[10] <= bits(RW0M, 10, 10)
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//~ ram.W_0.mask[11] <= bits(RW0M, 11, 11)
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//~ ram.W_0.mask[12] <= bits(RW0M, 12, 12)
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//~ ram.W_0.mask[13] <= bits(RW0M, 13, 13)
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//~ ram.W_0.mask[14] <= bits(RW0M, 14, 14)
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//~ ram.W_0.mask[15] <= bits(RW0M, 15, 15)
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//~ module vendor_sram_4 :
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class Synflops2048x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
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//~ input clock : Clock
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override lazy val memDepth = 2048
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//~ input RW0A : UInt<11>
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override lazy val memWidth = 16
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//~ input RW0I : UInt<4>
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//~ output RW0O : UInt<4>
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//~ input RW0E : UInt<1>
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//~ input RW0W : UInt<1>
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//~ input RW0M : UInt<4>
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//~ mem ram :
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compileExecuteAndTest(mem, None, v, output, true)
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//~ data-type => UInt<1>[4]
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}
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//~ depth => 2048
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//~ read-latency => 0
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//~ write-latency => 1
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//~ reader => R_0
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//~ writer => W_0
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//~ read-under-write => undefined
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//~ reg R_0_addr_reg : UInt<11>, clock with :
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//~ reset => (UInt<1>("h0"), R_0_addr_reg)
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//~ ram.R_0.clk <= clock
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//~ ram.R_0.addr <= R_0_addr_reg
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//~ ram.R_0.en <= RW0E
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//~ RW0O <= cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))
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//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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//~ ram.W_0.clk <= clock
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//~ ram.W_0.addr <= RW0A
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//~ ram.W_0.en <= and(RW0E, RW0W)
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//~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
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//~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
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//~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
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//~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
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//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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//~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
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|
||||||
//~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
|
|
||||||
//~ """
|
|
||||||
//~ compile(mem, None, v, true)
|
|
||||||
//~ execute(Some(mem), None, true, output)
|
|
||||||
//~ }
|
|
||||||
|
|
||||||
//~ class Synflops32x32_2rw extends MacroCompilerSpec {
|
class Synflops8192x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
|
||||||
//~ val mem = new File(macroDir, "lib-32x32-2rw.json")
|
override lazy val memDepth = 8192
|
||||||
//~ val v = new File(testDir, "syn_flops_32x32_2rw.v")
|
override lazy val memWidth = 16
|
||||||
//~ val output =
|
|
||||||
//~ """
|
|
||||||
//~ circuit SRAM2RW32x32 :
|
|
||||||
//~ module SRAM2RW32x32 :
|
|
||||||
//~ input CE1 : Clock
|
|
||||||
//~ input A1 : UInt<5>
|
|
||||||
//~ input I1 : UInt<32>
|
|
||||||
//~ output O1 : UInt<32>
|
|
||||||
//~ input CSB1 : UInt<1>
|
|
||||||
//~ input OEB1 : UInt<1>
|
|
||||||
//~ input WEB1 : UInt<1>
|
|
||||||
//~ input CE2 : Clock
|
|
||||||
//~ input A2 : UInt<5>
|
|
||||||
//~ input I2 : UInt<32>
|
|
||||||
//~ output O2 : UInt<32>
|
|
||||||
//~ input CSB2 : UInt<1>
|
|
||||||
//~ input OEB2 : UInt<1>
|
|
||||||
//~ input WEB2 : UInt<1>
|
|
||||||
|
|
||||||
//~ mem ram :
|
compileExecuteAndTest(mem, None, v, output, true)
|
||||||
//~ data-type => UInt<32>
|
}
|
||||||
//~ depth => 32
|
|
||||||
//~ read-latency => 0
|
class Synflops2048x16_depth_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
|
||||||
//~ write-latency => 1
|
override lazy val memDepth = 2048
|
||||||
//~ reader => R_0
|
override lazy val libDepth = 1024
|
||||||
//~ reader => R_1
|
override lazy val width = 16
|
||||||
//~ writer => W_0
|
|
||||||
//~ writer => W_1
|
compileExecuteAndTest(mem, lib, v, output, true)
|
||||||
//~ read-under-write => undefined
|
}
|
||||||
//~ reg R_0_addr_reg : UInt<5>, CE1 with :
|
|
||||||
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
|
class Synflops2048x64_width_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator with HasSynFlopsTestGenerator {
|
||||||
//~ ram.R_0.clk <= CE1
|
override lazy val memWidth = 64
|
||||||
//~ ram.R_0.addr <= R_0_addr_reg
|
override lazy val libWidth = 8
|
||||||
//~ ram.R_0.en <= and(not(CSB1), not(OEB1))
|
override lazy val depth = 1024
|
||||||
//~ O1 <= ram.R_0.data
|
|
||||||
//~ R_0_addr_reg <= mux(and(not(CSB1), not(OEB1)), A1, R_0_addr_reg)
|
compileExecuteAndTest(mem, lib, v, output, true)
|
||||||
//~ reg R_1_addr_reg : UInt<5>, CE2 with :
|
}
|
||||||
//~ reset => (UInt<1>("h0"), R_1_addr_reg)
|
|
||||||
//~ ram.R_1.clk <= CE2
|
class Synflops_SplitPorts_Read_Write extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
|
||||||
//~ ram.R_1.addr <= R_1_addr_reg
|
import mdf.macrolib._
|
||||||
//~ ram.R_1.en <= and(not(CSB2), not(OEB2))
|
|
||||||
//~ O2 <= ram.R_1.data
|
override lazy val memDepth = 2048
|
||||||
//~ R_1_addr_reg <= mux(and(not(CSB2), not(OEB2)), A2, R_1_addr_reg)
|
override lazy val libDepth = 1024
|
||||||
//~ ram.W_0.clk <= CE1
|
override lazy val width = 8
|
||||||
//~ ram.W_0.addr <= A1
|
|
||||||
//~ ram.W_0.en <= and(not(CSB1), not(WEB1))
|
override def generateLibSRAM = SRAMMacro(
|
||||||
//~ ram.W_0.data <= I1
|
macroType=SRAM,
|
||||||
//~ ram.W_0.mask <= UInt<1>("h1")
|
name=lib_name,
|
||||||
//~ ram.W_1.clk <= CE2
|
width=width,
|
||||||
//~ ram.W_1.addr <= A2
|
depth=libDepth,
|
||||||
//~ ram.W_1.en <= and(not(CSB2), not(WEB2))
|
family="1r1w",
|
||||||
//~ ram.W_1.data <= I2
|
ports=Seq(
|
||||||
//~ ram.W_1.mask <= UInt<1>("h1")
|
generateReadPort("innerA", width, libDepth),
|
||||||
//~ """
|
generateWritePort("innerB", width, libDepth)
|
||||||
//~ compile(mem, None, v, true)
|
)
|
||||||
//~ execute(Some(mem), None, true, output)
|
)
|
||||||
//~ }
|
|
||||||
|
override def generateMemSRAM = SRAMMacro(
|
||||||
|
macroType=SRAM,
|
||||||
|
name=mem_name,
|
||||||
|
width=width,
|
||||||
|
depth=memDepth,
|
||||||
|
family="1r1w",
|
||||||
|
ports=Seq(
|
||||||
|
generateReadPort("outerB", width, memDepth),
|
||||||
|
generateWritePort("outerA", width, memDepth)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
override def generateHeader =
|
||||||
|
"""
|
||||||
|
circuit target_memory :
|
||||||
|
module target_memory :
|
||||||
|
input outerB_clk : Clock
|
||||||
|
input outerB_addr : UInt<11>
|
||||||
|
output outerB_dout : UInt<8>
|
||||||
|
input outerA_clk : Clock
|
||||||
|
input outerA_addr : UInt<11>
|
||||||
|
input outerA_din : UInt<8>
|
||||||
|
input outerA_write_en : UInt<1>
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateBody =
|
||||||
|
"""
|
||||||
|
node outerB_addr_sel = bits(outerB_addr, 10, 10)
|
||||||
|
reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
|
||||||
|
reset => (UInt<1>("h0"), outerB_addr_sel_reg)
|
||||||
|
outerB_addr_sel_reg <= mux(UInt<1>("h1"), outerB_addr_sel, outerB_addr_sel_reg)
|
||||||
|
node outerA_addr_sel = bits(outerA_addr, 10, 10)
|
||||||
|
inst mem_0_0 of awesome_lib_mem
|
||||||
|
mem_0_0.innerB_clk <= outerA_clk
|
||||||
|
mem_0_0.innerB_addr <= outerA_addr
|
||||||
|
mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
|
||||||
|
mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
|
||||||
|
mem_0_0.innerA_clk <= outerB_clk
|
||||||
|
mem_0_0.innerA_addr <= outerB_addr
|
||||||
|
node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
|
||||||
|
node outerB_dout_0 = outerB_dout_0_0
|
||||||
|
inst mem_1_0 of awesome_lib_mem
|
||||||
|
mem_1_0.innerB_clk <= outerA_clk
|
||||||
|
mem_1_0.innerB_addr <= outerA_addr
|
||||||
|
mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
|
||||||
|
mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
|
||||||
|
mem_1_0.innerA_clk <= outerB_clk
|
||||||
|
mem_1_0.innerA_addr <= outerB_addr
|
||||||
|
node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
|
||||||
|
node outerB_dout_1 = outerB_dout_1_0
|
||||||
|
outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateFooterPorts =
|
||||||
|
"""
|
||||||
|
input innerA_clk : Clock
|
||||||
|
input innerA_addr : UInt<10>
|
||||||
|
output innerA_dout : UInt<8>
|
||||||
|
input innerB_clk : Clock
|
||||||
|
input innerB_addr : UInt<10>
|
||||||
|
input innerB_din : UInt<8>
|
||||||
|
input innerB_write_en : UInt<1>
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateFlops =
|
||||||
|
"""
|
||||||
|
mem ram :
|
||||||
|
data-type => UInt<8>
|
||||||
|
depth => 1024
|
||||||
|
read-latency => 1
|
||||||
|
write-latency => 1
|
||||||
|
reader => R_0
|
||||||
|
writer => W_0
|
||||||
|
read-under-write => undefined
|
||||||
|
ram.R_0.clk <= innerA_clk
|
||||||
|
ram.R_0.addr <= innerA_addr
|
||||||
|
ram.R_0.en <= UInt<1>("h1")
|
||||||
|
innerA_dout <= ram.R_0.data
|
||||||
|
ram.W_0.clk <= innerB_clk
|
||||||
|
ram.W_0.addr <= innerB_addr
|
||||||
|
ram.W_0.en <= innerB_write_en
|
||||||
|
ram.W_0.data <= innerB_din
|
||||||
|
ram.W_0.mask <= UInt<1>("h1")
|
||||||
|
"""
|
||||||
|
|
||||||
|
"Non-masked split lib; split mem" should "syn flops fine" in {
|
||||||
|
compileExecuteAndTest(mem, lib, v, output, true)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
|
||||||
|
import mdf.macrolib._
|
||||||
|
|
||||||
|
override lazy val memDepth = 2048
|
||||||
|
override lazy val libDepth = 1024
|
||||||
|
override lazy val width = 8
|
||||||
|
override lazy val memMaskGran = Some(8)
|
||||||
|
override lazy val libMaskGran = Some(1)
|
||||||
|
|
||||||
|
override def generateLibSRAM = SRAMMacro(
|
||||||
|
macroType=SRAM,
|
||||||
|
name=lib_name,
|
||||||
|
width=width,
|
||||||
|
depth=libDepth,
|
||||||
|
family="1r1w",
|
||||||
|
ports=Seq(
|
||||||
|
generateReadPort("innerA", width, libDepth),
|
||||||
|
generateWritePort("innerB", width, libDepth, libMaskGran)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
override def generateMemSRAM = SRAMMacro(
|
||||||
|
macroType=SRAM,
|
||||||
|
name=mem_name,
|
||||||
|
width=width,
|
||||||
|
depth=memDepth,
|
||||||
|
family="1r1w",
|
||||||
|
ports=Seq(
|
||||||
|
generateReadPort("outerB", width, memDepth),
|
||||||
|
generateWritePort("outerA", width, memDepth, memMaskGran)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
override def generateHeader =
|
||||||
|
"""
|
||||||
|
circuit target_memory :
|
||||||
|
module target_memory :
|
||||||
|
input outerB_clk : Clock
|
||||||
|
input outerB_addr : UInt<11>
|
||||||
|
output outerB_dout : UInt<8>
|
||||||
|
input outerA_clk : Clock
|
||||||
|
input outerA_addr : UInt<11>
|
||||||
|
input outerA_din : UInt<8>
|
||||||
|
input outerA_write_en : UInt<1>
|
||||||
|
input outerA_mask : UInt<1>
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateBody =
|
||||||
|
"""
|
||||||
|
node outerB_addr_sel = bits(outerB_addr, 10, 10)
|
||||||
|
reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
|
||||||
|
reset => (UInt<1>("h0"), outerB_addr_sel_reg)
|
||||||
|
outerB_addr_sel_reg <= mux(UInt<1>("h1"), outerB_addr_sel, outerB_addr_sel_reg)
|
||||||
|
node outerA_addr_sel = bits(outerA_addr, 10, 10)
|
||||||
|
inst mem_0_0 of awesome_lib_mem
|
||||||
|
mem_0_0.innerB_clk <= outerA_clk
|
||||||
|
mem_0_0.innerB_addr <= outerA_addr
|
||||||
|
mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
|
||||||
|
mem_0_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
|
||||||
|
mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
|
||||||
|
mem_0_0.innerA_clk <= outerB_clk
|
||||||
|
mem_0_0.innerA_addr <= outerB_addr
|
||||||
|
node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
|
||||||
|
node outerB_dout_0 = outerB_dout_0_0
|
||||||
|
inst mem_1_0 of awesome_lib_mem
|
||||||
|
mem_1_0.innerB_clk <= outerA_clk
|
||||||
|
mem_1_0.innerB_addr <= outerA_addr
|
||||||
|
mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
|
||||||
|
mem_1_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
|
||||||
|
mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
|
||||||
|
mem_1_0.innerA_clk <= outerB_clk
|
||||||
|
mem_1_0.innerA_addr <= outerB_addr
|
||||||
|
node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
|
||||||
|
node outerB_dout_1 = outerB_dout_1_0
|
||||||
|
outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateFooterPorts =
|
||||||
|
"""
|
||||||
|
input innerA_clk : Clock
|
||||||
|
input innerA_addr : UInt<10>
|
||||||
|
output innerA_dout : UInt<8>
|
||||||
|
input innerB_clk : Clock
|
||||||
|
input innerB_addr : UInt<10>
|
||||||
|
input innerB_din : UInt<8>
|
||||||
|
input innerB_write_en : UInt<1>
|
||||||
|
input innerB_mask : UInt<8>
|
||||||
|
"""
|
||||||
|
|
||||||
|
override def generateFlops =
|
||||||
|
"""
|
||||||
|
mem ram :
|
||||||
|
data-type => UInt<1>[8]
|
||||||
|
depth => 1024
|
||||||
|
read-latency => 1
|
||||||
|
write-latency => 1
|
||||||
|
reader => R_0
|
||||||
|
writer => W_0
|
||||||
|
read-under-write => undefined
|
||||||
|
ram.R_0.clk <= innerA_clk
|
||||||
|
ram.R_0.addr <= innerA_addr
|
||||||
|
ram.R_0.en <= UInt<1>("h1")
|
||||||
|
innerA_dout <= cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))
|
||||||
|
ram.W_0.clk <= innerB_clk
|
||||||
|
ram.W_0.addr <= innerB_addr
|
||||||
|
ram.W_0.en <= innerB_write_en
|
||||||
|
ram.W_0.data[0] <= bits(innerB_din, 0, 0)
|
||||||
|
ram.W_0.data[1] <= bits(innerB_din, 1, 1)
|
||||||
|
ram.W_0.data[2] <= bits(innerB_din, 2, 2)
|
||||||
|
ram.W_0.data[3] <= bits(innerB_din, 3, 3)
|
||||||
|
ram.W_0.data[4] <= bits(innerB_din, 4, 4)
|
||||||
|
ram.W_0.data[5] <= bits(innerB_din, 5, 5)
|
||||||
|
ram.W_0.data[6] <= bits(innerB_din, 6, 6)
|
||||||
|
ram.W_0.data[7] <= bits(innerB_din, 7, 7)
|
||||||
|
ram.W_0.mask[0] <= bits(innerB_mask, 0, 0)
|
||||||
|
ram.W_0.mask[1] <= bits(innerB_mask, 1, 1)
|
||||||
|
ram.W_0.mask[2] <= bits(innerB_mask, 2, 2)
|
||||||
|
ram.W_0.mask[3] <= bits(innerB_mask, 3, 3)
|
||||||
|
ram.W_0.mask[4] <= bits(innerB_mask, 4, 4)
|
||||||
|
ram.W_0.mask[5] <= bits(innerB_mask, 5, 5)
|
||||||
|
ram.W_0.mask[6] <= bits(innerB_mask, 6, 6)
|
||||||
|
ram.W_0.mask[7] <= bits(innerB_mask, 7, 7)
|
||||||
|
"""
|
||||||
|
|
||||||
|
"masked split lib; masked split mem" should "syn flops fine" in {
|
||||||
|
compileExecuteAndTest(mem, lib, v, output, true)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user