335 lines
11 KiB
Scala
335 lines
11 KiB
Scala
package barstools.macros
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// Use this trait for tests that invoke the memory compiler without lib.
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trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
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this: MacroCompilerSpec with HasSRAMGenerator =>
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// If there isn't a lib, then the "lib" will become a FIRRTL "mem", which
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// in turn becomes synthesized flops.
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// Therefore, make "lib" width/depth equal to the mem.
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override lazy val libDepth = memDepth
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override lazy val libWidth = memWidth
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// Do the same for port names.
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override lazy val libPortPrefix = memPortPrefix
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// If there is no lib, don't generate a body.
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override def generateBody = ""
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}
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// Test flop synthesis of the memory compiler.
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trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {
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this: MacroCompilerSpec with HasSRAMGenerator =>
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def generateFlops: String = {
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s"""
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mem ram :
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data-type => UInt<${libWidth}>
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depth => ${libDepth}
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read-latency => 1
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write-latency => 1
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readwriter => RW_0
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read-under-write => undefined
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ram.RW_0.clk <= ${libPortPrefix}_clk
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ram.RW_0.addr <= ${libPortPrefix}_addr
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ram.RW_0.en <= UInt<1>("h1")
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ram.RW_0.wmode <= ${libPortPrefix}_write_en
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${libPortPrefix}_dout <= ram.RW_0.rdata
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ram.RW_0.wdata <= ${libPortPrefix}_din
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ram.RW_0.wmask <= UInt<1>("h1")
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"""
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}
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// If there is no lib, put the flops definition into the body.
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abstract override def generateBody = {
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if (this.isInstanceOf[HasNoLibTestGenerator]) generateFlops else super.generateBody
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}
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// If there is no lib, don't generate a footer, since the flops definition
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// will be in the body.
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override def generateFooter = {
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if (this.isInstanceOf[HasNoLibTestGenerator]) "" else
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s"""
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module ${lib_name} :
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${generateFooterPorts}
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${generateFlops}
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"""
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}
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}
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class Synflops2048x8_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
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override lazy val memDepth = 2048
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override lazy val memWidth = 8
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compileExecuteAndTest(mem, None, v, output, true)
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}
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class Synflops2048x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
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override lazy val memDepth = 2048
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override lazy val memWidth = 16
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compileExecuteAndTest(mem, None, v, output, true)
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}
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class Synflops8192x16_noLib extends MacroCompilerSpec with HasSRAMGenerator with HasNoLibTestGenerator with HasSynFlopsTestGenerator {
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override lazy val memDepth = 8192
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override lazy val memWidth = 16
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compileExecuteAndTest(mem, None, v, output, true)
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}
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class Synflops2048x16_depth_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
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override lazy val memDepth = 2048
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override lazy val libDepth = 1024
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override lazy val width = 16
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compileExecuteAndTest(mem, lib, v, output, true)
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}
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class Synflops2048x64_width_Lib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator with HasSynFlopsTestGenerator {
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override lazy val memWidth = 64
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override lazy val libWidth = 8
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override lazy val depth = 1024
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compileExecuteAndTest(mem, lib, v, output, true)
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}
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class Synflops_SplitPorts_Read_Write extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
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import mdf.macrolib._
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override lazy val memDepth = 2048
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override lazy val libDepth = 1024
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override lazy val width = 8
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override def generateLibSRAM = SRAMMacro(
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macroType=SRAM,
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name=lib_name,
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width=width,
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depth=libDepth,
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family="1r1w",
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ports=Seq(
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generateReadPort("innerA", width, libDepth),
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generateWritePort("innerB", width, libDepth)
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)
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)
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override def generateMemSRAM = SRAMMacro(
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macroType=SRAM,
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name=mem_name,
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width=width,
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depth=memDepth,
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family="1r1w",
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ports=Seq(
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generateReadPort("outerB", width, memDepth),
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generateWritePort("outerA", width, memDepth)
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)
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)
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override def generateHeader =
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"""
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circuit target_memory :
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module target_memory :
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input outerB_clk : Clock
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input outerB_addr : UInt<11>
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output outerB_dout : UInt<8>
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input outerA_clk : Clock
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input outerA_addr : UInt<11>
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input outerA_din : UInt<8>
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input outerA_write_en : UInt<1>
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"""
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override def generateBody =
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"""
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node outerB_addr_sel = bits(outerB_addr, 10, 10)
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reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
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reset => (UInt<1>("h0"), outerB_addr_sel_reg)
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outerB_addr_sel_reg <= mux(UInt<1>("h1"), outerB_addr_sel, outerB_addr_sel_reg)
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node outerA_addr_sel = bits(outerA_addr, 10, 10)
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inst mem_0_0 of awesome_lib_mem
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mem_0_0.innerB_clk <= outerA_clk
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mem_0_0.innerB_addr <= outerA_addr
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mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
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mem_0_0.innerA_clk <= outerB_clk
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mem_0_0.innerA_addr <= outerB_addr
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node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
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node outerB_dout_0 = outerB_dout_0_0
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inst mem_1_0 of awesome_lib_mem
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mem_1_0.innerB_clk <= outerA_clk
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mem_1_0.innerB_addr <= outerA_addr
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mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
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mem_1_0.innerA_clk <= outerB_clk
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mem_1_0.innerA_addr <= outerB_addr
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node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
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node outerB_dout_1 = outerB_dout_1_0
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outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
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"""
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override def generateFooterPorts =
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"""
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input innerA_clk : Clock
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input innerA_addr : UInt<10>
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output innerA_dout : UInt<8>
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input innerB_clk : Clock
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input innerB_addr : UInt<10>
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input innerB_din : UInt<8>
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input innerB_write_en : UInt<1>
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"""
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override def generateFlops =
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"""
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mem ram :
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data-type => UInt<8>
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depth => 1024
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read-latency => 1
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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ram.R_0.clk <= innerA_clk
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ram.R_0.addr <= innerA_addr
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ram.R_0.en <= UInt<1>("h1")
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innerA_dout <= ram.R_0.data
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ram.W_0.clk <= innerB_clk
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ram.W_0.addr <= innerB_addr
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ram.W_0.en <= innerB_write_en
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ram.W_0.data <= innerB_din
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ram.W_0.mask <= UInt<1>("h1")
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"""
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"Non-masked split lib; split mem" should "syn flops fine" in {
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compileExecuteAndTest(mem, lib, v, output, true)
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}
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}
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class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator with HasSynFlopsTestGenerator {
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import mdf.macrolib._
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override lazy val memDepth = 2048
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override lazy val libDepth = 1024
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override lazy val width = 8
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override lazy val memMaskGran = Some(8)
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override lazy val libMaskGran = Some(1)
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override def generateLibSRAM = SRAMMacro(
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macroType=SRAM,
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name=lib_name,
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width=width,
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depth=libDepth,
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family="1r1w",
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ports=Seq(
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generateReadPort("innerA", width, libDepth),
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generateWritePort("innerB", width, libDepth, libMaskGran)
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)
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)
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override def generateMemSRAM = SRAMMacro(
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macroType=SRAM,
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name=mem_name,
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width=width,
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depth=memDepth,
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family="1r1w",
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ports=Seq(
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generateReadPort("outerB", width, memDepth),
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generateWritePort("outerA", width, memDepth, memMaskGran)
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)
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)
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override def generateHeader =
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"""
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circuit target_memory :
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module target_memory :
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input outerB_clk : Clock
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input outerB_addr : UInt<11>
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output outerB_dout : UInt<8>
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input outerA_clk : Clock
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input outerA_addr : UInt<11>
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input outerA_din : UInt<8>
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input outerA_write_en : UInt<1>
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input outerA_mask : UInt<1>
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"""
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override def generateBody =
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"""
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node outerB_addr_sel = bits(outerB_addr, 10, 10)
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reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
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reset => (UInt<1>("h0"), outerB_addr_sel_reg)
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outerB_addr_sel_reg <= mux(UInt<1>("h1"), outerB_addr_sel, outerB_addr_sel_reg)
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node outerA_addr_sel = bits(outerA_addr, 10, 10)
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inst mem_0_0 of awesome_lib_mem
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mem_0_0.innerB_clk <= outerA_clk
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mem_0_0.innerB_addr <= outerA_addr
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mem_0_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_0_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
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mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0")))
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mem_0_0.innerA_clk <= outerB_clk
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mem_0_0.innerA_addr <= outerB_addr
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node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
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node outerB_dout_0 = outerB_dout_0_0
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inst mem_1_0 of awesome_lib_mem
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mem_1_0.innerB_clk <= outerA_clk
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mem_1_0.innerB_addr <= outerA_addr
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mem_1_0.innerB_din <= bits(outerA_din, 7, 0)
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mem_1_0.innerB_mask <= cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), cat(bits(outerA_mask, 0, 0), bits(outerA_mask, 0, 0))))))))
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mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1")))
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mem_1_0.innerA_clk <= outerB_clk
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mem_1_0.innerA_addr <= outerB_addr
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node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
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node outerB_dout_1 = outerB_dout_1_0
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outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
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"""
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override def generateFooterPorts =
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"""
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input innerA_clk : Clock
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input innerA_addr : UInt<10>
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output innerA_dout : UInt<8>
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input innerB_clk : Clock
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input innerB_addr : UInt<10>
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input innerB_din : UInt<8>
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input innerB_write_en : UInt<1>
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input innerB_mask : UInt<8>
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"""
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override def generateFlops =
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"""
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mem ram :
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data-type => UInt<1>[8]
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depth => 1024
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read-latency => 1
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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ram.R_0.clk <= innerA_clk
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ram.R_0.addr <= innerA_addr
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ram.R_0.en <= UInt<1>("h1")
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innerA_dout <= cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))
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ram.W_0.clk <= innerB_clk
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ram.W_0.addr <= innerB_addr
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ram.W_0.en <= innerB_write_en
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ram.W_0.data[0] <= bits(innerB_din, 0, 0)
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ram.W_0.data[1] <= bits(innerB_din, 1, 1)
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ram.W_0.data[2] <= bits(innerB_din, 2, 2)
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ram.W_0.data[3] <= bits(innerB_din, 3, 3)
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ram.W_0.data[4] <= bits(innerB_din, 4, 4)
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ram.W_0.data[5] <= bits(innerB_din, 5, 5)
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ram.W_0.data[6] <= bits(innerB_din, 6, 6)
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ram.W_0.data[7] <= bits(innerB_din, 7, 7)
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ram.W_0.mask[0] <= bits(innerB_mask, 0, 0)
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ram.W_0.mask[1] <= bits(innerB_mask, 1, 1)
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ram.W_0.mask[2] <= bits(innerB_mask, 2, 2)
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ram.W_0.mask[3] <= bits(innerB_mask, 3, 3)
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ram.W_0.mask[4] <= bits(innerB_mask, 4, 4)
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ram.W_0.mask[5] <= bits(innerB_mask, 5, 5)
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ram.W_0.mask[6] <= bits(innerB_mask, 6, 6)
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ram.W_0.mask[7] <= bits(innerB_mask, 7, 7)
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"""
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"masked split lib; masked split mem" should "syn flops fine" in {
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compileExecuteAndTest(mem, lib, v, output, true)
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}
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}
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