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This commit is contained in:
abejgonzalez
2020-10-14 14:49:22 -07:00
parent 341a6cc48d
commit dda7622c29
8 changed files with 529 additions and 702 deletions
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28
fpga/src/main/scala/vcu118/Configs.scala
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@@ -23,20 +23,18 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD}
import chipyard.{BuildTop}
import chipyard.fpga.vcu118.bringup.{BringupGPIOs}
class WithChipyardBuildTop extends Config((site, here, up) => {
case DesignKey => {(p: Parameters) => new VCU118Platform()(p) }
})
import chipyard.harness._
class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = BigInt(0x64000000L)),
UARTParams(address = BigInt(0x64003000L)))
case PeripherySPIKey => List(
SPIParams(rAddress = BigInt(0x64001000L)),
SPIParams(rAddress = BigInt(0x64004000L)))
case VCU118ShellPMOD => "SDIO"
case PeripheryI2CKey => List(
I2CParams(address = BigInt(0x64005000L)))
// case PeripherySPIKey => List(
// SPIParams(rAddress = BigInt(0x64001000L)),
// SPIParams(rAddress = BigInt(0x64004000L)))
// case VCU118ShellPMOD => "SDIO"
// case PeripheryI2CKey => List(
// I2CParams(address = BigInt(0x64005000L)))
case PeripheryGPIOKey => {
if (BringupGPIOs.width > 0) {
require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
@@ -72,8 +70,18 @@ class SmallModifications extends Config((site, here, up) => {
class FakeBringupConfig extends Config(
new WithBringupUART ++
//new WithBringupSPI ++
//new WithBringupI2C ++
new WithBringupGPIO ++
new chipyard.iobinders.WithUARTIOCells ++
//new WithSPICells ++
//new WithI2CCells ++
new chipyard.iobinders.WithGPIOCells ++
//new WithBringupDDR ++
new WithBringupPeripherals ++
new WithChipyardBuildTop ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++

81
fpga/src/main/scala/vcu118/Platform.scala
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@@ -1,81 +0,0 @@
package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import chipyard.{BuildSystem}
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
trait HasVCU118PlatformIO {
val io_uart: Seq[UARTPortIO]
val io_spi: Seq[SPIPortIO]
val io_i2c: Seq[I2CPort]
val io_gpio: Seq[GPIOPortIO]
val io_tl_mem: HeterogeneousBag[TLBundle]
}
class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope {
val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// add MMC to the DTS
lazySystem match { case lsys: HasPeripherySPI =>
val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1)
ResourceBinding {
Resource(mmcDev, "reg").bind(ResourceAddress(0))
}
}
override lazy val module = new VCU118PlatformModule(this)
}
class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer)
with HasVCU118PlatformIO {
val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp =>
val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") }
(io_uart_pins_temp zip sys.uart).map { case (io, sysio) =>
io <> sysio
}
io_uart_pins_temp
}
val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp =>
val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") }
(io_spi_pins_temp zip sys.spi).map { case (io, sysio) =>
io <> sysio
}
io_spi_pins_temp
}
val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp =>
val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") }
(io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) =>
io <> sysio
}
io_i2c_pins_temp
}
val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp =>
val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") }
(io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) =>
io <> sysio
}
io_gpio_pins_temp
}
val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort =>
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> sys.mem_tl
io_tl_mem_pins_temp
}
}

130
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -19,10 +19,12 @@ import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer}
import chipyard.harness._
import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions}
case object DUTFrequencyKey extends Field[Double](100.0)
class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell {
class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences {
def dp = designParameters
@@ -58,122 +60,20 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar
}
}
/*** UART ***/
require(dp(PeripheryUARTKey).size == 2)
lazy val harnessClock = InModuleBody {
dutClock.in.head._1.clock
}.getWrappedValue
lazy val harnessReset = InModuleBody {
WireInit(dutClock.in.head._1.reset)
}.getWrappedValue
lazy val dutReset = harnessReset
lazy val success = InModuleBody { false.B }.getWrappedValue
// 1st UART goes to the VCU118 dedicated UART
// BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design
// to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level.
val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_uart_bb.bundle <> dutMod.io_uart.head
topDesign match { case d: HasTestHarnessFunctions =>
InModuleBody {
d.harnessFunctions.foreach(_(this))
}
ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap)
}
// 2nd UART goes to the FMC UART
val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_uart_bb_2.bundle <> dutMod.io_uart.last
}
}
/*** SPI ***/
require(dp(PeripherySPIKey).size == 2)
// 1st SPI goes to the VCU118 SDIO port
val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb.bundle <> dutMod.io_spi.head
}
}
// TODO: No access to the TLSPI node...
//val mmcDev = new MMCDevice(sdio_placed.device, 1)
//ResourceBinding {
// Resource(mmcDev, "reg").bind(ResourceAddress(0))
//}
// 2nd SPI goes to the ADI port
val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb_2.bundle <> dutMod.io_spi.last
}
}
// TODO: No access to the TLSPI node...
//val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1)
//ResourceBinding {
// Resource(adiDev, "reg").bind(ResourceAddress(0))
//}
/*** I2C ***/
require(dp(PeripheryI2CKey).size == 1)
val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_i2c_bb.bundle <> dutMod.io_i2c.head
}
}
/*** GPIO ***/
val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
val maxGPIOSupport = 32
val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
})
val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
placer.place(GPIODesignInput(params, io_gpio_bb(i)))
}
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
(io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) =>
bb_io.bundle <> dut_io
}
}
}
/*** Experimental DDR ***/
val ddrWrangler = LazyModule(new ResetWrangler)
val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL))
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: VCU118Platform =>
td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(inParams.master))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
val bundles = ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
ddrClientBundle <> dutMod.io_tl_mem
}
}
ddrPlaced.overlayOutput.ddr := ddrClient
}