From dda7622c29c1bd00abdb74bcd7251915886ed323 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 14 Oct 2020 14:49:22 -0700 Subject: [PATCH] temp commit --- fpga/src/main/scala/arty/TestHarness.scala | 68 +- fpga/src/main/scala/arty/e300/Configs.scala | 144 ++-- .../src/main/scala/arty/e300/DigitalTop.scala | 46 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 730 +++++++++--------- fpga/src/main/scala/vcu118/Configs.scala | 28 +- fpga/src/main/scala/vcu118/Platform.scala | 81 -- fpga/src/main/scala/vcu118/TestHarness.scala | 130 +--- .../chipyard/src/main/scala/ChipTop.scala | 4 +- 8 files changed, 529 insertions(+), 702 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/Platform.scala diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..6571f3d6 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -1,34 +1,34 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{Analog} - -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - -import chipyard.{BuildTop, HasHarnessSignalReferences} - -class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { - - val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - - // turn IO clock into Reset type - val hReset = Wire(Reset()) - hReset := ck_rst - - // default to 32MHz clock - withClockAndReset(clock_32MHz, hReset) { - val dut = Module(ldut.module) - } - - val harnessClock = clock_32MHz - val harnessReset = hReset - val success = false.B - val dutReset = hReset - - // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) -} - +//package chipyard.fpga.arty +// +//import chisel3._ +//import chisel3.experimental.{Analog} +// +//import freechips.rocketchip.diplomacy.{LazyModule} +//import freechips.rocketchip.config.{Parameters} +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +// +//import chipyard.{BuildTop, HasHarnessSignalReferences} +// +//class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { +// +// val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") +// +// // turn IO clock into Reset type +// val hReset = Wire(Reset()) +// hReset := ck_rst +// +// // default to 32MHz clock +// withClockAndReset(clock_32MHz, hReset) { +// val dut = Module(ldut.module) +// } +// +// val harnessClock = clock_32MHz +// val harnessReset = hReset +// val success = false.B +// val dutReset = hReset +// +// // must be after HasHarnessSignalReferences assignments +// ldut.harnessFunctions.foreach(_(this)) +//} +// diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..9e04d8df 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,72 +1,72 @@ -// See LICENSE for license details. -package chipyard.fpga.arty.e300 - -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} -import freechips.rocketchip.system._ -import freechips.rocketchip.tile._ - -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.i2c._ - -import chipyard.{BuildSystem} - -class E300DevKitExtra extends Config((site, here, up) => { - case PeripheryGPIOKey => List( - GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) - case PeripheryPWMKey => List( - PWMParams(address = 0x10015000, cmpWidth = 8), - PWMParams(address = 0x10025000, cmpWidth = 16), - PWMParams(address = 0x10035000, cmpWidth = 16)) - case PeripherySPIKey => List( - SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), - SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) - case PeripherySPIFlashKey => List( - SPIFlashParams( - fAddress = 0x20000000, - rAddress = 0x10014000, - defaultSampleDel = 3)) - case PeripheryUARTKey => List( - UARTParams(address = 0x10013000), - UARTParams(address = 0x10023000)) - case PeripheryI2CKey => List( - I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) - case DTSTimebase => BigInt(32768) - case JtagDTMKey => new JtagDTMConfig ( - idcodeVersion = 2, - idcodePartNum = 0x000, - idcodeManufId = 0x489, - debugIdleCycles = 5) -}) - -class WithE300System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) -}) - -class E300ArtyDevKitConfig extends Config( - new WithE300System ++ - new WithE300Connections ++ - new E300DevKitExtra ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) +//// See LICENSE for license details. +//package chipyard.fpga.arty.e300 +// +//import freechips.rocketchip.config._ +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.devices.tilelink._ +//import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} +//import freechips.rocketchip.system._ +//import freechips.rocketchip.tile._ +// +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.i2c._ +// +//import chipyard.{BuildSystem} +// +//class E300DevKitExtra extends Config((site, here, up) => { +// case PeripheryGPIOKey => List( +// GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) +// case PeripheryPWMKey => List( +// PWMParams(address = 0x10015000, cmpWidth = 8), +// PWMParams(address = 0x10025000, cmpWidth = 16), +// PWMParams(address = 0x10035000, cmpWidth = 16)) +// case PeripherySPIKey => List( +// SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3), +// SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3)) +// case PeripherySPIFlashKey => List( +// SPIFlashParams( +// fAddress = 0x20000000, +// rAddress = 0x10014000, +// defaultSampleDel = 3)) +// case PeripheryUARTKey => List( +// UARTParams(address = 0x10013000), +// UARTParams(address = 0x10023000)) +// case PeripheryI2CKey => List( +// I2CParams(address = 0x10016000)) +// case PeripheryMockAONKey => +// MockAONParams(address = 0x10000000) +// case DTSTimebase => BigInt(32768) +// case JtagDTMKey => new JtagDTMConfig ( +// idcodeVersion = 2, +// idcodePartNum = 0x000, +// idcodeManufId = 0x489, +// debugIdleCycles = 5) +//}) +// +//class WithE300System extends Config((site, here, up) => { +// case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +//}) +// +//class E300ArtyDevKitConfig extends Config( +// new WithE300System ++ +// new WithE300Connections ++ +// new E300DevKitExtra ++ +// new chipyard.config.WithBootROM ++ +// new chipyard.config.WithL2TLBs(1024) ++ +// new freechips.rocketchip.subsystem.With1TinyCore ++ +// new freechips.rocketchip.subsystem.WithNBanks(0) ++ +// new freechips.rocketchip.subsystem.WithNoMemPort ++ +// new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ +// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ +// new freechips.rocketchip.subsystem.WithJtagDTM ++ +// new freechips.rocketchip.subsystem.WithNoMMIOPort ++ +// new freechips.rocketchip.subsystem.WithNoSlavePort ++ +// new freechips.rocketchip.subsystem.WithInclusiveCache ++ +// new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ +// new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ +// new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..45018c00 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -1,23 +1,23 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.devices.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// E300 DigitalTop -// ------------------------------------ - -class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON -{ - override lazy val module = new E300DigitalTopModule(this) -} - -class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +// +//import freechips.rocketchip.subsystem._ +//import freechips.rocketchip.system._ +//import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.devices.tilelink._ +// +//import chipyard.{DigitalTop, DigitalTopModule} +// +//// ------------------------------------ +//// E300 DigitalTop +//// ------------------------------------ +// +//class E300DigitalTop(implicit p: Parameters) extends DigitalTop +// with sifive.blocks.devices.mockaon.HasPeripheryMockAON +//{ +// override lazy val module = new E300DigitalTopModule(this) +//} +// +//class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) +// with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..82da669c 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,365 +1,365 @@ -package chipyard.fpga.arty.e300 - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - io_aon <> system.aon.pins - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - +//package chipyard.fpga.arty.e300 +// +//import chisel3._ +//import chisel3.experimental.{attach, IO} +// +//import freechips.rocketchip.util._ +//import freechips.rocketchip.devices.debug._ +//import freechips.rocketchip.subsystem.{NExtTopInterrupts} +// +//import sifive.blocks.devices.gpio._ +//import sifive.blocks.devices.uart._ +//import sifive.blocks.devices.spi._ +//import sifive.blocks.devices.pwm._ +//import sifive.blocks.devices.i2c._ +//import sifive.blocks.devices.mockaon._ +//import sifive.blocks.devices.jtag._ +//import sifive.blocks.devices.pinctrl._ +// +//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} +//import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} +// +//import chipsalliance.rocketchip.config._ +// +//import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} +//import chipyard.{HasHarnessSignalReferences} +// +//class WithE300Connections extends OverrideIOBinder({ +// (system: HasPeripheryGPIOModuleImp +// with HasPeripheryUARTModuleImp +// with HasPeripherySPIModuleImp +// with HasPeripheryDebugModuleImp +// with HasPeripheryPWMModuleImp +// with HasPeripherySPIFlashModuleImp +// with HasPeripheryMockAONModuleImp +// with HasPeripheryI2CModuleImp) => { +// +// implicit val p: Parameters = GetSystemParameters(system) +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // E300DigitalTop <-> ChipTop connections +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// +// object PinGen { +// def apply(): BasePin = { +// val pin = new BasePin() +// pin +// } +// } +// +// val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") +// val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") +// val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") +// val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") +// val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") +// val io_ndreset = IO(Output(Bool())).suggestName("ndreset") +// +// // This needs to be de-asserted synchronously to the coreClk. +// val async_corerst = system.aon.rsts.corerst +// // Add in debug-controlled reset. +// system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) +// Debug.connectDebugClockAndReset(system.debug, system.clock) +// +// //----------------------------------------------------------------------- +// // Check for unsupported rocket-chip connections +// //----------------------------------------------------------------------- +// +// require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); +// +// //----------------------------------------------------------------------- +// // Build GPIO Pin Mux +// //----------------------------------------------------------------------- +// // Pin Mux for UART, SPI, PWM +// // First convert the System outputs into "IOF" using the respective *GPIOPort +// // converters. +// +// val sys_uart = system.uart +// val sys_pwm = system.pwm +// val sys_spi = system.spi +// val sys_i2c = system.i2c +// +// val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} +// val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} +// val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} +// val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} +// +// (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } +// (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} +// +// //----------------------------------------------------------------------- +// // Default Pin connections before attaching pinmux +// +// for (iof_0 <- system.gpio(0).iof_0.get) { +// iof_0.default() +// } +// +// for (iof_1 <- system.gpio(0).iof_1.get) { +// iof_1.default() +// } +// +// //----------------------------------------------------------------------- +// +// val iof_0 = system.gpio(0).iof_0.get +// val iof_1 = system.gpio(0).iof_1.get +// +// // SPI1 (0 is the dedicated) +// BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) +// BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) +// BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) +// BasePinToIOF(spi_pins(0).sck, iof_0(5)) +// BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) +// BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) +// BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) +// BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) +// BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) +// +// // SPI2 +// BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) +// BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) +// BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) +// BasePinToIOF(spi_pins(1).sck, iof_0(29)) +// BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) +// BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) +// +// // I2C +// if (p(PeripheryI2CKey).length == 1) { +// BasePinToIOF(i2c_pins(0).sda, iof_0(12)) +// BasePinToIOF(i2c_pins(0).scl, iof_0(13)) +// } +// +// // UART0 +// BasePinToIOF(uart_pins(0).rxd, iof_0(16)) +// BasePinToIOF(uart_pins(0).txd, iof_0(17)) +// +// // UART1 +// BasePinToIOF(uart_pins(1).rxd, iof_0(24)) +// BasePinToIOF(uart_pins(1).txd, iof_0(25)) +// +// //PWM +// BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) +// BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) +// BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) +// BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) +// +// BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) +// BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) +// BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) +// BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) +// +// BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) +// BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) +// BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) +// BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) +// +// //----------------------------------------------------------------------- +// // Drive actual Pads +// //----------------------------------------------------------------------- +// +// // Result of Pin Mux +// GPIOPinsFromPort(io_gpio, system.gpio(0)) +// +// // Dedicated SPI Pads +// SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) +// +// // JTAG Debug Interface +// val sjtag = system.debug.get.systemjtag.get +// JTAGPinsFromPort(io_jtag, sjtag.jtag) +// sjtag.reset := io_jtag_reset +// sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) +// +// io_ndreset := system.debug.get.ndreset +// +// // AON Pads -- direct connection is OK because +// // EnhancedPin is hard-coded in MockAONPads +// // and thus there is no .fromPort method. +// io_aon <> system.aon.pins +// +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// // Harness Function (ArtyHarness <-> ChipTop) +// //----------------------------------------------------------------------- +// //----------------------------------------------------------------------- +// val harnessFn = (baseTh: HasHarnessSignalReferences) => { +// baseTh match { case th: ArtyShell => +// +// //----------------------------------------------------------------------- +// // Clock divider +// //----------------------------------------------------------------------- +// val slow_clock = Wire(Bool()) +// +// // Divide clock by 256, used to generate 32.768 kHz clock for AON block +// withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { +// val clockToggleReg = RegInit(false.B) +// val (_, slowTick) = chisel3.util.Counter(true.B, 256) +// when (slowTick) {clockToggleReg := ~clockToggleReg} +// slow_clock := clockToggleReg +// } +// +// //----------------------------------------------------------------------- +// // DUT +// //----------------------------------------------------------------------- +// withClockAndReset(th.clock_32MHz, th.ck_rst) { +// +// //--------------------------------------------------------------------- +// // SPI flash IOBUFs +// //--------------------------------------------------------------------- +// +// IOBUF(th.qspi_sck, io_qspi.sck) +// IOBUF(th.qspi_cs, io_qspi.cs(0)) +// +// IOBUF(th.qspi_dq(0), io_qspi.dq(0)) +// IOBUF(th.qspi_dq(1), io_qspi.dq(1)) +// IOBUF(th.qspi_dq(2), io_qspi.dq(2)) +// IOBUF(th.qspi_dq(3), io_qspi.dq(3)) +// +// //--------------------------------------------------------------------- +// // JTAG IOBUFs +// //--------------------------------------------------------------------- +// +// io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt +// +// IOBUF(th.jd_5, io_jtag.TMS) +// PULLUP(th.jd_5) +// +// IOBUF(th.jd_4, io_jtag.TDI) +// PULLUP(th.jd_4) +// +// IOBUF(th.jd_0, io_jtag.TDO) +// +// // mimic putting a pullup on this line (part of reset vote) +// th.SRST_n := IOBUF(th.jd_6) +// PULLUP(th.jd_6) +// +// // jtag reset +// val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) +// io_jtag_reset := jtag_power_on_reset +// +// // debug reset +// th.dut_ndreset := io_ndreset +// +// //--------------------------------------------------------------------- +// // Assignment to package pins +// //--------------------------------------------------------------------- +// // Pins IO0-IO13 +// // +// // FTDI UART TX/RX are not connected to th.ck_io[0,1] +// // the way they are on Arduino boards. We copy outgoing +// // data to both places, switch 3 (sw[3]) determines whether +// // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) +// +// val iobuf_ck0 = Module(new IOBUF()) +// iobuf_ck0.io.I := io_gpio.pins(16).o.oval +// iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX +// +// val iobuf_uart_txd = Module(new IOBUF()) +// iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval +// iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe +// attach(iobuf_uart_txd.io.IO, th.uart_txd_in) +// +// // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] +// val sw_3_in = IOBUF(th.sw_3) +// io_gpio.pins(16).i.ival := Mux(sw_3_in, +// iobuf_ck0.io.O & io_gpio.pins(16).o.ie, +// iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) +// +// IOBUF(th.uart_rxd_out, io_gpio.pins(17)) +// +// // Shield header row 0: PD2-PD7 +// IOBUF(th.ck_io(2), io_gpio.pins(18)) +// IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) +// IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) +// IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) +// IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) +// IOBUF(th.ck_io(7), io_gpio.pins(23)) +// +// // Header row 1: PB0-PB5 +// IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) +// IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) +// IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) +// IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) +// IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO +// IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK +// +// io_gpio.pins(6).i.ival := 0.U +// io_gpio.pins(7).i.ival := 0.U +// io_gpio.pins(8).i.ival := 0.U +// +// // Header row 3: A0-A5 (we don't support using them as analog inputs) +// // just treat them as regular digital GPIOs +// IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) +// IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) +// IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) +// IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA +// IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL +// +// // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty +// // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active +// IOBUF(th.led0_r, io_gpio.pins(1)) +// IOBUF(th.led0_g, io_gpio.pins(2)) +// IOBUF(th.led0_b, io_gpio.pins(3)) +// +// // Note that this is the one which is actually connected on the HiFive/Crazy88 +// // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active +// IOBUF(th.led1_r, io_gpio.pins(19)) +// IOBUF(th.led1_g, io_gpio.pins(21)) +// IOBUF(th.led1_b, io_gpio.pins(22)) +// +// // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active +// IOBUF(th.led2_r, io_gpio.pins(11)) +// IOBUF(th.led2_g, io_gpio.pins(12)) +// IOBUF(th.led2_b, io_gpio.pins(13)) +// +// // Only 19 out of 20 shield pins connected to GPIO pins +// // Shield pin A5 (pin 14) left unconnected +// // The buttons are connected to some extra GPIO pins not connected on the +// // HiFive1 board +// IOBUF(th.btn_0, io_gpio.pins(15)) +// IOBUF(th.btn_1, io_gpio.pins(30)) +// IOBUF(th.btn_2, io_gpio.pins(31)) +// +// val iobuf_btn_3 = Module(new IOBUF()) +// iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval +// iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe +// attach(th.btn_3, iobuf_btn_3.io.IO) +// io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie +// +// // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 +// IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX +// IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX +// +// // SPI2 pins mapped to 6 pin ICSP connector (standard on later +// // arduinos) These are connected to some extra GPIO pins not connected +// // on the HiFive1 board +// IOBUF(th.ck_ss, io_gpio.pins(26)) +// IOBUF(th.ck_mosi, io_gpio.pins(27)) +// IOBUF(th.ck_miso, io_gpio.pins(28)) +// IOBUF(th.ck_sck, io_gpio.pins(29)) +// +// // Use the LEDs for some more useful debugging things +// IOBUF(th.led_0, th.ck_rst) +// IOBUF(th.led_1, th.SRST_n) +// IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) +// IOBUF(th.led_3, io_gpio.pins(14)) +// +// //--------------------------------------------------------------------- +// // Unconnected inputs +// //--------------------------------------------------------------------- +// +// io_aon.erst_n.i.ival := ~th.reset_periph +// io_aon.lfextclk.i.ival := slow_clock +// io_aon.pmu.vddpaden.i.ival := 1.U +// } +// +// Nil +// } +// } +// +// Seq((Nil, Nil, Some(harnessFn))) +// } +//}) +// diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ab087afa..feaa0484 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -23,20 +23,18 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} import chipyard.fpga.vcu118.bringup.{BringupGPIOs} -class WithChipyardBuildTop extends Config((site, here, up) => { - case DesignKey => {(p: Parameters) => new VCU118Platform()(p) } -}) +import chipyard.harness._ class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) - case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), - SPIParams(rAddress = BigInt(0x64004000L))) - case VCU118ShellPMOD => "SDIO" - case PeripheryI2CKey => List( - I2CParams(address = BigInt(0x64005000L))) +// case PeripherySPIKey => List( +// SPIParams(rAddress = BigInt(0x64001000L)), +// SPIParams(rAddress = BigInt(0x64004000L))) +// case VCU118ShellPMOD => "SDIO" +// case PeripheryI2CKey => List( +// I2CParams(address = BigInt(0x64005000L))) case PeripheryGPIOKey => { if (BringupGPIOs.width > 0) { require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) @@ -72,8 +70,18 @@ class SmallModifications extends Config((site, here, up) => { class FakeBringupConfig extends Config( + new WithBringupUART ++ + //new WithBringupSPI ++ + //new WithBringupI2C ++ + new WithBringupGPIO ++ + new chipyard.iobinders.WithUARTIOCells ++ + //new WithSPICells ++ + //new WithI2CCells ++ + new chipyard.iobinders.WithGPIOCells ++ + //new WithBringupDDR ++ new WithBringupPeripherals ++ - new WithChipyardBuildTop ++ + new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ diff --git a/fpga/src/main/scala/vcu118/Platform.scala b/fpga/src/main/scala/vcu118/Platform.scala deleted file mode 100644 index 342f7328..00000000 --- a/fpga/src/main/scala/vcu118/Platform.scala +++ /dev/null @@ -1,81 +0,0 @@ -package chipyard.fpga.vcu118 - -import chisel3._ -import chisel3.experimental.{Analog, IO, DataMirror} - -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import chipyard.{BuildSystem} - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -trait HasVCU118PlatformIO { - val io_uart: Seq[UARTPortIO] - val io_spi: Seq[SPIPortIO] - val io_i2c: Seq[I2CPort] - val io_gpio: Seq[GPIOPortIO] - val io_tl_mem: HeterogeneousBag[TLBundle] -} - -class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope { - - val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") - - // add MMC to the DTS - lazySystem match { case lsys: HasPeripherySPI => - val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1) - ResourceBinding { - Resource(mmcDev, "reg").bind(ResourceAddress(0)) - } - } - - override lazy val module = new VCU118PlatformModule(this) -} - -class VCU118PlatformModule[+L <: VCU118Platform](_outer: L) extends LazyModuleImp(_outer) - with HasVCU118PlatformIO { - - val io_uart = _outer.lazySystem.module match { case sys: HasPeripheryUARTModuleImp => - val io_uart_pins_temp = p(PeripheryUARTKey).zipWithIndex.map { case (p, i) => IO(new UARTPortIO(p)).suggestName(s"uart_$i") } - (io_uart_pins_temp zip sys.uart).map { case (io, sysio) => - io <> sysio - } - io_uart_pins_temp - } - - val io_spi = _outer.lazySystem.module match { case sys: HasPeripherySPIModuleImp => - val io_spi_pins_temp = p(PeripherySPIKey).zipWithIndex.map { case (p, i) => IO(new SPIPortIO(p)).suggestName(s"spi_$i") } - (io_spi_pins_temp zip sys.spi).map { case (io, sysio) => - io <> sysio - } - io_spi_pins_temp - } - - val io_i2c = _outer.lazySystem.module match { case sys: HasPeripheryI2CModuleImp => - val io_i2c_pins_temp = p(PeripheryI2CKey).zipWithIndex.map { case (p, i) => IO(new I2CPort).suggestName(s"i2c_$i") } - (io_i2c_pins_temp zip sys.i2c).map { case (io, sysio) => - io <> sysio - } - io_i2c_pins_temp - } - - val io_gpio = _outer.lazySystem.module match { case sys: HasPeripheryGPIOModuleImp => - val io_gpio_pins_temp = p(PeripheryGPIOKey).zipWithIndex.map { case (p, i) => IO(new GPIOPortIO(p)).suggestName(s"gpio_$i") } - (io_gpio_pins_temp zip sys.gpio).map { case (io, sysio) => - io <> sysio - } - io_gpio_pins_temp - } - - val io_tl_mem = _outer.lazySystem match { case sys: chipyard.CanHaveMasterTLMemPort => - val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](sys.mem_tl)).suggestName("tl_slave") - io_tl_mem_pins_temp <> sys.mem_tl - io_tl_mem_pins_temp - } -} diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 4275f68d..d371aced 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -19,10 +19,12 @@ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} +import chipyard.harness._ +import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions} case object DUTFrequencyKey extends Field[Double](100.0) -class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell { +class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell with HasHarnessSignalReferences { def dp = designParameters @@ -58,122 +60,20 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends Chipyar } } - /*** UART ***/ - require(dp(PeripheryUARTKey).size == 2) + lazy val harnessClock = InModuleBody { + dutClock.in.head._1.clock + }.getWrappedValue + lazy val harnessReset = InModuleBody { + WireInit(dutClock.in.head._1.reset) + }.getWrappedValue + lazy val dutReset = harnessReset + lazy val success = InModuleBody { false.B }.getWrappedValue - // 1st UART goes to the VCU118 dedicated UART - - // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design - // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level. - val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) - dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb.bundle <> dutMod.io_uart.head + topDesign match { case d: HasTestHarnessFunctions => + InModuleBody { + d.harnessFunctions.foreach(_(this)) } + ApplyHarnessBinders(this, d.lazySystem, d.portMap.toMap) } - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_uart_bb_2.bundle <> dutMod.io_uart.last - } - } - - /*** SPI ***/ - require(dp(PeripherySPIKey).size == 2) - - // 1st SPI goes to the VCU118 SDIO port - - val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head))) - val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb.bundle <> dutMod.io_spi.head - } - } - - // TODO: No access to the TLSPI node... - //val mmcDev = new MMCDevice(sdio_placed.device, 1) - //ResourceBinding { - // Resource(mmcDev, "reg").bind(ResourceAddress(0)) - //} - - // 2nd SPI goes to the ADI port - - val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput())) - - val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last))) - val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_spi_bb_2.bundle <> dutMod.io_spi.last - } - } - - // TODO: No access to the TLSPI node... - //val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1) - //ResourceBinding { - // Resource(adiDev, "reg").bind(ResourceAddress(0)) - //} - - /*** I2C ***/ - require(dp(PeripheryI2CKey).size == 1) - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - io_i2c_bb.bundle <> dutMod.io_i2c.head - } - } - - /*** GPIO ***/ - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - (io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) => - bb_io.bundle <> dut_io - } - } - } - - /*** Experimental DDR ***/ - - val ddrWrangler = LazyModule(new ResetWrangler) - val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL)) - - // connect 1 mem. channel to the FPGA DDR - val inParams = topDesign match { case td: VCU118Platform => - td.lazySystem match { case lsys: chipyard.CanHaveMasterTLMemPort => - lsys.memTLNode.edges.in(0) - } - } - val ddrClient = TLClientNode(Seq(inParams.master)) - InModuleBody { - topDesign.module match { case dutMod: HasVCU118PlatformIO => - val bundles = ddrClient.out.map(_._1) - val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType))) - bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io } - ddrClientBundle <> dutMod.io_tl_mem - } - } - ddrPlaced.overlayOutput.ddr := ddrClient } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 1cef2180..b86b6b07 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.iobinders._ @@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions { +class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunctions with BindingScope { // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) val iocells = ArrayBuffer.empty[IOCell]