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small fixes for sim yaml generation

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This commit is contained in:
Nayiri K
2023-06-30 15:04:04 -07:00
parent 2ba1198842
commit dcaca02e14
1 changed files with 2 additions and 2 deletions
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4
vlsi/sim.mk
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@@ -21,7 +21,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
done done
echo " options_meta: 'append'" >> $@ echo " options_meta: 'append'" >> $@
echo " defines:" >> $@ echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ for x in $(subst +define+,,$(SIM_PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " defines_meta: 'append'" >> $@ echo " defines_meta: 'append'" >> $@
@@ -75,7 +75,7 @@ $(SIM_TIMING_CONF): $(sim_common_files)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@ echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@ echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@ echo " timing_annotated: true" >> $@
# Update hammer top-level sim targets to include our generated sim configs # Update hammer top-level sim targets to include our generated sim configs
redo-sim-rtl: $(SIM_CONF) redo-sim-rtl: $(SIM_CONF)