From dcaca02e1488d99b93d101e07ec7edd6f6b5fb93 Mon Sep 17 00:00:00 2001
From: Nayiri K <nayiri@berkeley.edu>
Date: Fri, 30 Jun 2023 15:04:04 -0700
Subject: [PATCH] small fixes for sim yaml generation

---
 vlsi/sim.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index b721c9fb..ea2c76d7 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -21,7 +21,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
 	done
 	echo "  options_meta: 'append'" >> $@
 	echo "  defines:" >> $@
-	for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
+	for x in $(subst +define+,,$(SIM_PREPROC_DEFINES)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  defines_meta: 'append'" >> $@
@@ -75,7 +75,7 @@ $(SIM_TIMING_CONF): $(sim_common_files)
 	echo "sim.inputs:" > $@
 	echo "  defines: ['NTC']" >> $@
 	echo "  defines_meta: 'append'" >> $@
-	echo "  timing_annotated: 'true'" >> $@
+	echo "  timing_annotated: true" >> $@
 
 # Update hammer top-level sim targets to include our generated sim configs
 redo-sim-rtl: $(SIM_CONF)