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Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.

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This commit is contained in:
James Dunn
2020-10-10 19:55:02 -07:00
parent 54acfe71fc
commit dca56cd858
4 changed files with 5 additions and 369 deletions
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4
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -31,7 +31,7 @@ import scala.reflect.{ClassTag}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => {
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
// (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
// ports.map {
// case d: ClockedDMIIO =>
@@ -63,7 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
})
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// UARTAdapter.connect(ports)(system.p)
// IOBUF(th.ck_io(2), ports.txd)