Fix CI tests
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@@ -34,11 +34,12 @@ object ResetN extends Pass {
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mod.copy(ports = portsx, body = bodyx)
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}
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def run(c: Circuit): Circuit =
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def run(c: Circuit): Circuit = {
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c.copy(modules = c.modules map {
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case mod: Module if mod.name == c.main => invertReset(mod)
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case other => other
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})
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}
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}
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class ResetInverterTransform extends Transform {
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