diff --git a/macros/src/test/scala/CostFunction.scala b/macros/src/test/scala/CostFunction.scala index c82080b2..35936ed1 100644 --- a/macros/src/test/scala/CostFunction.scala +++ b/macros/src/test/scala/CostFunction.scala @@ -82,22 +82,22 @@ circuit target_memory : mem_0_0.addr <= addr node dout_0_0 = bits(mem_0_0.dout, 31, 0) mem_0_0.din <= bits(din, 31, 0) - mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.clk <= clk mem_0_1.addr <= addr node dout_0_1 = bits(mem_0_1.dout, 31, 0) mem_0_1.din <= bits(din, 63, 32) - mem_0_1.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.clk <= clk mem_0_2.addr <= addr node dout_0_2 = bits(mem_0_2.dout, 31, 0) mem_0_2.din <= bits(din, 95, 64) - mem_0_2.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.clk <= clk mem_0_3.addr <= addr node dout_0_3 = bits(mem_0_3.dout, 31, 0) mem_0_3.din <= bits(din, 127, 96) - mem_0_3.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node dout_0 = cat(dout_0_3, cat(dout_0_2, cat(dout_0_1, dout_0_0))) dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0")) diff --git a/macros/src/test/scala/MultiPort.scala b/macros/src/test/scala/MultiPort.scala index 470fee16..fdaae9f7 100644 --- a/macros/src/test/scala/MultiPort.scala +++ b/macros/src/test/scala/MultiPort.scala @@ -66,50 +66,50 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim node portA_dout_0_0 = bits(mem_0_0.portA_dout, 15, 0) mem_0_0.portA_din <= bits(portA_din, 15, 0) mem_0_0.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_0.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portA_clk <= portA_clk mem_0_1.portA_addr <= portA_addr node portA_dout_0_1 = bits(mem_0_1.portA_dout, 15, 0) mem_0_1.portA_din <= bits(portA_din, 31, 16) mem_0_1.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_1.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portA_clk <= portA_clk mem_0_2.portA_addr <= portA_addr node portA_dout_0_2 = bits(mem_0_2.portA_dout, 15, 0) mem_0_2.portA_din <= bits(portA_din, 47, 32) mem_0_2.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_2.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portA_clk <= portA_clk mem_0_3.portA_addr <= portA_addr node portA_dout_0_3 = bits(mem_0_3.portA_dout, 15, 0) mem_0_3.portA_din <= bits(portA_din, 63, 48) mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_3.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) node portA_dout_0 = cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0))) mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr node portB_dout_0_0 = bits(mem_0_0.portB_dout, 15, 0) mem_0_0.portB_din <= bits(portB_din, 15, 0) mem_0_0.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr node portB_dout_0_1 = bits(mem_0_1.portB_dout, 15, 0) mem_0_1.portB_din <= bits(portB_din, 31, 16) mem_0_1.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr node portB_dout_0_2 = bits(mem_0_2.portB_dout, 15, 0) mem_0_2.portB_din <= bits(portB_din, 47, 32) mem_0_2.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr node portB_dout_0_3 = bits(mem_0_3.portB_dout, 15, 0) mem_0_3.portB_din <= bits(portB_din, 63, 48) mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))) portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) @@ -185,19 +185,19 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr mem_0_0.portB_din <= bits(portB_din, 15, 0) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr mem_0_1.portB_din <= bits(portB_din, 31, 16) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr mem_0_2.portB_din <= bits(portB_din, 47, 32) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr mem_0_3.portB_din <= bits(portB_din, 63, 48) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) mem_0_0.portA_clk <= portA_clk mem_0_0.portA_addr <= portA_addr node portA_dout_0_0 = bits(mem_0_0.portA_dout, 15, 0) @@ -291,98 +291,98 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera node portA_dout_0_0 = bits(mem_0_0.portA_dout, 7, 0) mem_0_0.portA_din <= bits(portA_din, 7, 0) mem_0_0.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_0.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portA_clk <= portA_clk mem_0_1.portA_addr <= portA_addr node portA_dout_0_1 = bits(mem_0_1.portA_dout, 7, 0) mem_0_1.portA_din <= bits(portA_din, 15, 8) mem_0_1.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_1.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_1.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_2.portA_clk <= portA_clk mem_0_2.portA_addr <= portA_addr node portA_dout_0_2 = bits(mem_0_2.portA_dout, 7, 0) mem_0_2.portA_din <= bits(portA_din, 23, 16) mem_0_2.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_2.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_2.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_3.portA_clk <= portA_clk mem_0_3.portA_addr <= portA_addr node portA_dout_0_3 = bits(mem_0_3.portA_dout, 7, 0) mem_0_3.portA_din <= bits(portA_din, 31, 24) mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_3.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_3.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_4.portA_clk <= portA_clk mem_0_4.portA_addr <= portA_addr node portA_dout_0_4 = bits(mem_0_4.portA_dout, 7, 0) mem_0_4.portA_din <= bits(portA_din, 39, 32) mem_0_4.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_4.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_4.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_5.portA_clk <= portA_clk mem_0_5.portA_addr <= portA_addr node portA_dout_0_5 = bits(mem_0_5.portA_dout, 7, 0) mem_0_5.portA_din <= bits(portA_din, 47, 40) mem_0_5.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_5.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_5.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_6.portA_clk <= portA_clk mem_0_6.portA_addr <= portA_addr node portA_dout_0_6 = bits(mem_0_6.portA_dout, 7, 0) mem_0_6.portA_din <= bits(portA_din, 55, 48) mem_0_6.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_6.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_6.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) mem_0_7.portA_clk <= portA_clk mem_0_7.portA_addr <= portA_addr node portA_dout_0_7 = bits(mem_0_7.portA_dout, 7, 0) mem_0_7.portA_din <= bits(portA_din, 63, 56) mem_0_7.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_7.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_7.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) node portA_dout_0 = cat(portA_dout_0_7, cat(portA_dout_0_6, cat(portA_dout_0_5, cat(portA_dout_0_4, cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0))))))) mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr node portB_dout_0_0 = bits(mem_0_0.portB_dout, 7, 0) mem_0_0.portB_din <= bits(portB_din, 7, 0) mem_0_0.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr node portB_dout_0_1 = bits(mem_0_1.portB_dout, 7, 0) mem_0_1.portB_din <= bits(portB_din, 15, 8) mem_0_1.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr node portB_dout_0_2 = bits(mem_0_2.portB_dout, 7, 0) mem_0_2.portB_din <= bits(portB_din, 23, 16) mem_0_2.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr node portB_dout_0_3 = bits(mem_0_3.portB_dout, 7, 0) mem_0_3.portB_din <= bits(portB_din, 31, 24) mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) mem_0_4.portB_clk <= portB_clk mem_0_4.portB_addr <= portB_addr node portB_dout_0_4 = bits(mem_0_4.portB_dout, 7, 0) mem_0_4.portB_din <= bits(portB_din, 39, 32) mem_0_4.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_4.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 4, 4)), UInt<1>("h1")) + mem_0_4.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 4, 4)), UInt<1>("h1")) mem_0_5.portB_clk <= portB_clk mem_0_5.portB_addr <= portB_addr node portB_dout_0_5 = bits(mem_0_5.portB_dout, 7, 0) mem_0_5.portB_din <= bits(portB_din, 47, 40) mem_0_5.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_5.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 5, 5)), UInt<1>("h1")) + mem_0_5.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 5, 5)), UInt<1>("h1")) mem_0_6.portB_clk <= portB_clk mem_0_6.portB_addr <= portB_addr node portB_dout_0_6 = bits(mem_0_6.portB_dout, 7, 0) mem_0_6.portB_din <= bits(portB_din, 55, 48) mem_0_6.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_6.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 6, 6)), UInt<1>("h1")) + mem_0_6.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 6, 6)), UInt<1>("h1")) mem_0_7.portB_clk <= portB_clk mem_0_7.portB_addr <= portB_addr node portB_dout_0_7 = bits(mem_0_7.portB_dout, 7, 0) mem_0_7.portB_din <= bits(portB_din, 63, 56) mem_0_7.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_7.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 7, 7)), UInt<1>("h1")) + mem_0_7.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 7, 7)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_7, cat(portB_dout_0_6, cat(portB_dout_0_5, cat(portB_dout_0_4, cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))))))) portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala index 18b4a930..8df8ec7e 100644 --- a/macros/src/test/scala/SimpleSplitDepth.scala +++ b/macros/src/test/scala/SimpleSplitDepth.scala @@ -31,6 +31,8 @@ s""" for (i <- 0 to depthInstances - 1) { val maskStatement = generateMaskStatement(0, i) val enableIdentifier = if (selectBits > 0) s"""eq(${memPortPrefix}_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")" + val chipEnable = s"""UInt<1>("h1")""" + val writeEnable = if (memMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en" output.append( s""" inst mem_${i}_0 of ${lib_name} @@ -39,7 +41,7 @@ s""" node ${memPortPrefix}_dout_${i}_0 = bits(mem_${i}_0.${libPortPrefix}_dout, ${width - 1}, 0) mem_${i}_0.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${width - 1}, 0) ${maskStatement} - mem_${i}_0.${libPortPrefix}_write_en <= and(and(${memPortPrefix}_write_en, UInt<1>("h1")), ${enableIdentifier}) + mem_${i}_0.${libPortPrefix}_write_en <= and(and(${writeEnable}, UInt<1>("h1")), ${enableIdentifier}) node ${memPortPrefix}_dout_${i} = ${memPortPrefix}_dout_${i}_0 """ ) @@ -273,7 +275,7 @@ circuit target_memory : node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0"))) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0"))) node outer_dout_0 = outer_dout_0_0 inst mem_1_0 of awesome_lib_mem @@ -283,7 +285,7 @@ circuit target_memory : node outer_dout_1_0 = bits(mem_1_0.lib_dout, 7, 0) mem_1_0.lib_din <= bits(outer_din, 7, 0) - mem_1_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1"))) + mem_1_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1"))) node outer_dout_1 = outer_dout_1_0 outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<1>("h0"))) extmodule awesome_lib_mem : @@ -362,7 +364,7 @@ circuit target_memory : mem_0_0.innerB_clk <= outerA_clk mem_0_0.innerB_addr <= outerA_addr mem_0_0.innerB_din <= bits(outerA_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) + mem_0_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) mem_0_0.innerA_clk <= outerB_clk mem_0_0.innerA_addr <= outerB_addr node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) @@ -371,7 +373,7 @@ circuit target_memory : mem_1_0.innerB_clk <= outerA_clk mem_1_0.innerB_addr <= outerA_addr mem_1_0.innerB_din <= bits(outerA_din, 7, 0) - mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) + mem_1_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) mem_1_0.innerA_clk <= outerB_clk mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) diff --git a/macros/src/test/scala/SimpleSplitWidth.scala b/macros/src/test/scala/SimpleSplitWidth.scala index 3d26c18d..9cc10f9d 100644 --- a/macros/src/test/scala/SimpleSplitWidth.scala +++ b/macros/src/test/scala/SimpleSplitWidth.scala @@ -38,6 +38,8 @@ trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator { val outerMaskBit = myBaseBit / memMaskGran.get s"bits(outer_mask, ${outerMaskBit}, ${outerMaskBit})" } else """UInt<1>("h1")""" + val chipEnable = s"""UInt<1>("h1")""" + val writeEnableExpr = if (libMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en" s""" mem_0_${i}.${libPortPrefix}_clk <= ${memPortPrefix}_clk @@ -45,7 +47,7 @@ s""" node ${memPortPrefix}_dout_0_${i} = bits(mem_0_${i}.${libPortPrefix}_dout, ${myMemWidth - 1}, 0) mem_0_${i}.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${myBaseBit + myMemWidth - 1}, ${myBaseBit}) ${maskStatement} - mem_0_${i}.${libPortPrefix}_write_en <= and(and(${memPortPrefix}_write_en, ${writeEnableBit}), UInt<1>("h1")) + mem_0_${i}.${libPortPrefix}_write_en <= and(and(${writeEnableExpr}, ${writeEnableBit}), UInt<1>("h1")) """ }).reduceLeft(_ + _) @@ -415,26 +417,26 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen mem_0_0.lib_addr <= outer_addr node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) - mem_0_0.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.lib_clk <= outer_clk mem_0_1.lib_addr <= outer_addr node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0) mem_0_1.lib_din <= bits(outer_din, 15, 8) - mem_0_1.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.lib_clk <= outer_clk mem_0_2.lib_addr <= outer_addr node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0) mem_0_2.lib_din <= bits(outer_din, 23, 16) - mem_0_2.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.lib_clk <= outer_clk mem_0_3.lib_addr <= outer_addr node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0) mem_0_3.lib_din <= bits(outer_din, 31, 24) - mem_0_3.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ @@ -514,25 +516,25 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) mem_0_0.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.lib_clk <= outer_clk mem_0_1.lib_addr <= outer_addr node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0) mem_0_1.lib_din <= bits(outer_din, 15, 8) mem_0_1.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.lib_clk <= outer_clk mem_0_2.lib_addr <= outer_addr node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0) mem_0_2.lib_din <= bits(outer_din, 23, 16) mem_0_2.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.lib_clk <= outer_clk mem_0_3.lib_addr <= outer_addr node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0) mem_0_3.lib_din <= bits(outer_din, 31, 24) mem_0_3.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ diff --git a/macros/src/test/scala/SpecificExamples.scala b/macros/src/test/scala/SpecificExamples.scala index 7179d20f..56f4500f 100644 --- a/macros/src/test/scala/SpecificExamples.scala +++ b/macros/src/test/scala/SpecificExamples.scala @@ -59,34 +59,34 @@ class WriteEnableTest extends MacroCompilerSpec with HasSRAMGenerator { val output = """ - circuit cc_banks_0_ext : - module cc_banks_0_ext : - input RW0_addr : UInt<12> - input RW0_clk : Clock - input RW0_wdata : UInt<64> - output RW0_rdata : UInt<64> - input RW0_en : UInt<1> - input RW0_wmode : UInt<1> +circuit cc_banks_0_ext : + module cc_banks_0_ext : + input RW0_addr : UInt<12> + input RW0_clk : Clock + input RW0_wdata : UInt<64> + output RW0_rdata : UInt<64> + input RW0_en : UInt<1> + input RW0_wmode : UInt<1> - inst mem_0_0 of fake_mem - mem_0_0.clk <= RW0_clk - mem_0_0.addr <= RW0_addr - node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) - mem_0_0.datain <= bits(RW0_wdata, 63, 0) - mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) - mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1")) - node RW0_rdata_0 = RW0_rdata_0_0 - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + inst mem_0_0 of fake_mem + mem_0_0.clk <= RW0_clk + mem_0_0.addr <= RW0_addr + node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) + mem_0_0.datain <= bits(RW0_wdata, 63, 0) + mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) + mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1")) + node RW0_rdata_0 = RW0_rdata_0_0 + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) - extmodule fake_mem : - input addr : UInt<12> - input clk : Clock - input datain : UInt<64> - output dataout : UInt<64> - input ren : UInt<1> - input wen : UInt<1> + extmodule fake_mem : + input addr : UInt<12> + input clk : Clock + input datain : UInt<64> + output dataout : UInt<64> + input ren : UInt<1> + input wen : UInt<1> - defname = fake_mem + defname = fake_mem """ compileExecuteAndTest(mem, lib, v, output) @@ -148,14 +148,14 @@ circuit cc_dir_ext : mem_0_0.addr <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) mem_0_0.datain <= bits(RW0_wdata, 63, 0) - mem_0_0.ren <= and(not(RW0_wmode), UInt<1>("h1")) + mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) mem_0_0.mport <= not(cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), bits(RW0_wmask, 0, 0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) mem_0_0.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1")) mem_0_1.clk <= RW0_clk mem_0_1.addr <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.dataout, 63, 0) mem_0_1.datain <= bits(RW0_wdata, 127, 64) - mem_0_1.ren <= and(not(RW0_wmode), UInt<1>("h1")) + mem_0_1.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) @@ -379,53 +379,53 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 21, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 43, 22) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.CE1 <= W0_clk mem_0_2.A1 <= W0_addr mem_0_2.I1 <= bits(W0_data, 65, 44) - mem_0_2.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_2.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.CE1 <= W0_clk mem_0_3.A1 <= W0_addr mem_0_3.I1 <= bits(W0_data, 87, 66) - mem_0_3.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_3.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 21, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 21, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.CE2 <= R0_clk mem_0_2.A2 <= R0_addr node R0_data_0_2 = bits(mem_0_2.O2, 21, 0) mem_0_2.I2 is invalid - mem_0_2.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_2.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.CE2 <= R0_clk mem_0_3.A2 <= R0_addr node R0_data_0_3 = bits(mem_0_3.O2, 21, 0) mem_0_3.I2 is invalid - mem_0_3.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_3.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0))) @@ -436,53 +436,53 @@ circuit smem_0_ext : mem_1_0.CE1 <= W0_clk mem_1_0.A1 <= W0_addr mem_1_0.I1 <= bits(W0_data, 21, 0) - mem_1_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.CE1 <= W0_clk mem_1_1.A1 <= W0_addr mem_1_1.I1 <= bits(W0_data, 43, 22) - mem_1_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.CE1 <= W0_clk mem_1_2.A1 <= W0_addr mem_1_2.I1 <= bits(W0_data, 65, 44) - mem_1_2.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_2.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.CE1 <= W0_clk mem_1_3.A1 <= W0_addr mem_1_3.I1 <= bits(W0_data, 87, 66) - mem_1_3.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_3.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.CE2 <= R0_clk mem_1_0.A2 <= R0_addr node R0_data_1_0 = bits(mem_1_0.O2, 21, 0) mem_1_0.I2 is invalid - mem_1_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.CE2 <= R0_clk mem_1_1.A2 <= R0_addr node R0_data_1_1 = bits(mem_1_1.O2, 21, 0) mem_1_1.I2 is invalid - mem_1_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.CE2 <= R0_clk mem_1_2.A2 <= R0_addr node R0_data_1_2 = bits(mem_1_2.O2, 21, 0) mem_1_2.I2 is invalid - mem_1_2.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_2.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.CE2 <= R0_clk mem_1_3.A2 <= R0_addr node R0_data_1_3 = bits(mem_1_3.O2, 21, 0) mem_1_3.I2 is invalid - mem_1_3.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_3.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) node R0_data_1 = cat(R0_data_1_3, cat(R0_data_1_2, cat(R0_data_1_1, R0_data_1_0))) @@ -510,27 +510,27 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 31, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h0")))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 63, 32) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h0")))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 31, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h0")))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 31, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h0")))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h0")))) node R0_data_0 = cat(R0_data_0_1, R0_data_0_0) @@ -539,27 +539,27 @@ circuit smem_0_ext : mem_1_0.CE1 <= W0_clk mem_1_0.A1 <= W0_addr mem_1_0.I1 <= bits(W0_data, 31, 0) - mem_1_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h1")))) + mem_1_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.CE1 <= W0_clk mem_1_1.A1 <= W0_addr mem_1_1.I1 <= bits(W0_data, 63, 32) - mem_1_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h1")))) + mem_1_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.CE2 <= R0_clk mem_1_0.A2 <= R0_addr node R0_data_1_0 = bits(mem_1_0.O2, 31, 0) mem_1_0.I2 is invalid - mem_1_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h1")))) + mem_1_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.CE2 <= R0_clk mem_1_1.A2 <= R0_addr node R0_data_1_1 = bits(mem_1_1.O2, 31, 0) mem_1_1.I2 is invalid - mem_1_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h1")))) + mem_1_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h1")))) node R0_data_1 = cat(R0_data_1_1, R0_data_1_0) @@ -568,27 +568,27 @@ circuit smem_0_ext : mem_2_0.CE1 <= W0_clk mem_2_0.A1 <= W0_addr mem_2_0.I1 <= bits(W0_data, 31, 0) - mem_2_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h2")))) + mem_2_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.CE1 <= W0_clk mem_2_1.A1 <= W0_addr mem_2_1.I1 <= bits(W0_data, 63, 32) - mem_2_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h2")))) + mem_2_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.CE2 <= R0_clk mem_2_0.A2 <= R0_addr node R0_data_2_0 = bits(mem_2_0.O2, 31, 0) mem_2_0.I2 is invalid - mem_2_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h2")))) + mem_2_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.CE2 <= R0_clk mem_2_1.A2 <= R0_addr node R0_data_2_1 = bits(mem_2_1.O2, 31, 0) mem_2_1.I2 is invalid - mem_2_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h2")))) + mem_2_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h2")))) node R0_data_2 = cat(R0_data_2_1, R0_data_2_0) @@ -597,27 +597,27 @@ circuit smem_0_ext : mem_3_0.CE1 <= W0_clk mem_3_0.A1 <= W0_addr mem_3_0.I1 <= bits(W0_data, 31, 0) - mem_3_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h3")))) + mem_3_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.CE1 <= W0_clk mem_3_1.A1 <= W0_addr mem_3_1.I1 <= bits(W0_data, 63, 32) - mem_3_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h3")))) + mem_3_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.CE2 <= R0_clk mem_3_0.A2 <= R0_addr node R0_data_3_0 = bits(mem_3_0.O2, 31, 0) mem_3_0.I2 is invalid - mem_3_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h3")))) + mem_3_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.CE2 <= R0_clk mem_3_1.A2 <= R0_addr node R0_data_3_1 = bits(mem_3_1.O2, 31, 0) mem_3_1.I2 is invalid - mem_3_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h3")))) + mem_3_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3")))) node R0_data_3 = cat(R0_data_3_1, R0_data_3_0) @@ -659,28 +659,28 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 19, 0) mem_0_0.I <= bits(RW0_wdata, 19, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 19, 0) mem_0_1.I <= bits(RW0_wdata, 39, 20) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 19, 0) mem_0_2.I <= bits(RW0_wdata, 59, 40) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 19, 0) mem_0_3.I <= bits(RW0_wdata, 79, 60) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))) @@ -712,14 +712,14 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 31, 0) mem_0_0.I <= bits(RW0_wdata, 31, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 31, 0) mem_0_1.I <= bits(RW0_wdata, 63, 32) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) @@ -752,27 +752,27 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 21, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1"))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), UInt<1>("h1"))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB1 <= not(and(W0_en, UInt<1>("h1"))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 39, 22) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1"))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), UInt<1>("h1"))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB1 <= not(and(W0_en, UInt<1>("h1"))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 21, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1"))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), UInt<1>("h1"))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB2 <= not(and(R0_en, UInt<1>("h1"))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 17, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1"))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), UInt<1>("h1"))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1"))) node R0_data_0 = cat(R0_data_0_1, R0_data_0_0) @@ -842,224 +842,224 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 0, 0) mem_0_0.I <= bits(RW0_wdata, 0, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 0, 0) mem_0_1.I <= bits(RW0_wdata, 1, 1) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 0, 0) mem_0_2.I <= bits(RW0_wdata, 2, 2) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 0, 0) mem_0_3.I <= bits(RW0_wdata, 3, 3) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_4.CE <= RW0_clk mem_0_4.A <= RW0_addr node RW0_rdata_0_4 = bits(mem_0_4.O, 0, 0) mem_0_4.I <= bits(RW0_wdata, 4, 4) - mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_4.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1"))) mem_0_4.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_5.CE <= RW0_clk mem_0_5.A <= RW0_addr node RW0_rdata_0_5 = bits(mem_0_5.O, 0, 0) mem_0_5.I <= bits(RW0_wdata, 5, 5) - mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_5.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1"))) mem_0_5.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_6.CE <= RW0_clk mem_0_6.A <= RW0_addr node RW0_rdata_0_6 = bits(mem_0_6.O, 0, 0) mem_0_6.I <= bits(RW0_wdata, 6, 6) - mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_6.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1"))) mem_0_6.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_7.CE <= RW0_clk mem_0_7.A <= RW0_addr node RW0_rdata_0_7 = bits(mem_0_7.O, 0, 0) mem_0_7.I <= bits(RW0_wdata, 7, 7) - mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_7.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))) mem_0_7.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_8.CE <= RW0_clk mem_0_8.A <= RW0_addr node RW0_rdata_0_8 = bits(mem_0_8.O, 0, 0) mem_0_8.I <= bits(RW0_wdata, 8, 8) - mem_0_8.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_8.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_8.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 8, 8)), UInt<1>("h1"))) mem_0_8.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_9.CE <= RW0_clk mem_0_9.A <= RW0_addr node RW0_rdata_0_9 = bits(mem_0_9.O, 0, 0) mem_0_9.I <= bits(RW0_wdata, 9, 9) - mem_0_9.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_9.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_9.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 9, 9)), UInt<1>("h1"))) mem_0_9.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_10.CE <= RW0_clk mem_0_10.A <= RW0_addr node RW0_rdata_0_10 = bits(mem_0_10.O, 0, 0) mem_0_10.I <= bits(RW0_wdata, 10, 10) - mem_0_10.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_10.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_10.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 10, 10)), UInt<1>("h1"))) mem_0_10.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_11.CE <= RW0_clk mem_0_11.A <= RW0_addr node RW0_rdata_0_11 = bits(mem_0_11.O, 0, 0) mem_0_11.I <= bits(RW0_wdata, 11, 11) - mem_0_11.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_11.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_11.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 11, 11)), UInt<1>("h1"))) mem_0_11.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_12.CE <= RW0_clk mem_0_12.A <= RW0_addr node RW0_rdata_0_12 = bits(mem_0_12.O, 0, 0) mem_0_12.I <= bits(RW0_wdata, 12, 12) - mem_0_12.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_12.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_12.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 12, 12)), UInt<1>("h1"))) mem_0_12.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_13.CE <= RW0_clk mem_0_13.A <= RW0_addr node RW0_rdata_0_13 = bits(mem_0_13.O, 0, 0) mem_0_13.I <= bits(RW0_wdata, 13, 13) - mem_0_13.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_13.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_13.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 13, 13)), UInt<1>("h1"))) mem_0_13.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_14.CE <= RW0_clk mem_0_14.A <= RW0_addr node RW0_rdata_0_14 = bits(mem_0_14.O, 0, 0) mem_0_14.I <= bits(RW0_wdata, 14, 14) - mem_0_14.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_14.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_14.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 14, 14)), UInt<1>("h1"))) mem_0_14.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_15.CE <= RW0_clk mem_0_15.A <= RW0_addr node RW0_rdata_0_15 = bits(mem_0_15.O, 0, 0) mem_0_15.I <= bits(RW0_wdata, 15, 15) - mem_0_15.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_15.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_15.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 15, 15)), UInt<1>("h1"))) mem_0_15.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_16.CE <= RW0_clk mem_0_16.A <= RW0_addr node RW0_rdata_0_16 = bits(mem_0_16.O, 0, 0) mem_0_16.I <= bits(RW0_wdata, 16, 16) - mem_0_16.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_16.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_16.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 16, 16)), UInt<1>("h1"))) mem_0_16.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_17.CE <= RW0_clk mem_0_17.A <= RW0_addr node RW0_rdata_0_17 = bits(mem_0_17.O, 0, 0) mem_0_17.I <= bits(RW0_wdata, 17, 17) - mem_0_17.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_17.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_17.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 17, 17)), UInt<1>("h1"))) mem_0_17.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_18.CE <= RW0_clk mem_0_18.A <= RW0_addr node RW0_rdata_0_18 = bits(mem_0_18.O, 0, 0) mem_0_18.I <= bits(RW0_wdata, 18, 18) - mem_0_18.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_18.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_18.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 18, 18)), UInt<1>("h1"))) mem_0_18.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_19.CE <= RW0_clk mem_0_19.A <= RW0_addr node RW0_rdata_0_19 = bits(mem_0_19.O, 0, 0) mem_0_19.I <= bits(RW0_wdata, 19, 19) - mem_0_19.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_19.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_19.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 19, 19)), UInt<1>("h1"))) mem_0_19.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_20.CE <= RW0_clk mem_0_20.A <= RW0_addr node RW0_rdata_0_20 = bits(mem_0_20.O, 0, 0) mem_0_20.I <= bits(RW0_wdata, 20, 20) - mem_0_20.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_20.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_20.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 20, 20)), UInt<1>("h1"))) mem_0_20.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_21.CE <= RW0_clk mem_0_21.A <= RW0_addr node RW0_rdata_0_21 = bits(mem_0_21.O, 0, 0) mem_0_21.I <= bits(RW0_wdata, 21, 21) - mem_0_21.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_21.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_21.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 21, 21)), UInt<1>("h1"))) mem_0_21.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_22.CE <= RW0_clk mem_0_22.A <= RW0_addr node RW0_rdata_0_22 = bits(mem_0_22.O, 0, 0) mem_0_22.I <= bits(RW0_wdata, 22, 22) - mem_0_22.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_22.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_22.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 22, 22)), UInt<1>("h1"))) mem_0_22.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_23.CE <= RW0_clk mem_0_23.A <= RW0_addr node RW0_rdata_0_23 = bits(mem_0_23.O, 0, 0) mem_0_23.I <= bits(RW0_wdata, 23, 23) - mem_0_23.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_23.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_23.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 23, 23)), UInt<1>("h1"))) mem_0_23.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_24.CE <= RW0_clk mem_0_24.A <= RW0_addr node RW0_rdata_0_24 = bits(mem_0_24.O, 0, 0) mem_0_24.I <= bits(RW0_wdata, 24, 24) - mem_0_24.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_24.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_24.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 24, 24)), UInt<1>("h1"))) mem_0_24.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_25.CE <= RW0_clk mem_0_25.A <= RW0_addr node RW0_rdata_0_25 = bits(mem_0_25.O, 0, 0) mem_0_25.I <= bits(RW0_wdata, 25, 25) - mem_0_25.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_25.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_25.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 25, 25)), UInt<1>("h1"))) mem_0_25.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_26.CE <= RW0_clk mem_0_26.A <= RW0_addr node RW0_rdata_0_26 = bits(mem_0_26.O, 0, 0) mem_0_26.I <= bits(RW0_wdata, 26, 26) - mem_0_26.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_26.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_26.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 26, 26)), UInt<1>("h1"))) mem_0_26.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_27.CE <= RW0_clk mem_0_27.A <= RW0_addr node RW0_rdata_0_27 = bits(mem_0_27.O, 0, 0) mem_0_27.I <= bits(RW0_wdata, 27, 27) - mem_0_27.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_27.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_27.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 27, 27)), UInt<1>("h1"))) mem_0_27.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_28.CE <= RW0_clk mem_0_28.A <= RW0_addr node RW0_rdata_0_28 = bits(mem_0_28.O, 0, 0) mem_0_28.I <= bits(RW0_wdata, 28, 28) - mem_0_28.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_28.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_28.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 28, 28)), UInt<1>("h1"))) mem_0_28.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_29.CE <= RW0_clk mem_0_29.A <= RW0_addr node RW0_rdata_0_29 = bits(mem_0_29.O, 0, 0) mem_0_29.I <= bits(RW0_wdata, 29, 29) - mem_0_29.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_29.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_29.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 29, 29)), UInt<1>("h1"))) mem_0_29.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_30.CE <= RW0_clk mem_0_30.A <= RW0_addr node RW0_rdata_0_30 = bits(mem_0_30.O, 0, 0) mem_0_30.I <= bits(RW0_wdata, 30, 30) - mem_0_30.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_30.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_30.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 30, 30)), UInt<1>("h1"))) mem_0_30.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_31.CE <= RW0_clk mem_0_31.A <= RW0_addr node RW0_rdata_0_31 = bits(mem_0_31.O, 0, 0) mem_0_31.I <= bits(RW0_wdata, 31, 31) - mem_0_31.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_31.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) @@ -1110,224 +1110,224 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 0, 0) mem_0_0.I <= bits(RW0_wdata, 0, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 0, 0) mem_0_1.I <= bits(RW0_wdata, 1, 1) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 0, 0) mem_0_2.I <= bits(RW0_wdata, 2, 2) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 0, 0) mem_0_3.I <= bits(RW0_wdata, 3, 3) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_4.CE <= RW0_clk mem_0_4.A <= RW0_addr node RW0_rdata_0_4 = bits(mem_0_4.O, 0, 0) mem_0_4.I <= bits(RW0_wdata, 4, 4) - mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_4.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1"))) mem_0_4.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_5.CE <= RW0_clk mem_0_5.A <= RW0_addr node RW0_rdata_0_5 = bits(mem_0_5.O, 0, 0) mem_0_5.I <= bits(RW0_wdata, 5, 5) - mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_5.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1"))) mem_0_5.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_6.CE <= RW0_clk mem_0_6.A <= RW0_addr node RW0_rdata_0_6 = bits(mem_0_6.O, 0, 0) mem_0_6.I <= bits(RW0_wdata, 6, 6) - mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_6.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1"))) mem_0_6.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_7.CE <= RW0_clk mem_0_7.A <= RW0_addr node RW0_rdata_0_7 = bits(mem_0_7.O, 0, 0) mem_0_7.I <= bits(RW0_wdata, 7, 7) - mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_7.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))) mem_0_7.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_8.CE <= RW0_clk mem_0_8.A <= RW0_addr node RW0_rdata_0_8 = bits(mem_0_8.O, 0, 0) mem_0_8.I <= bits(RW0_wdata, 8, 8) - mem_0_8.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_8.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_8.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 8, 8)), UInt<1>("h1"))) mem_0_8.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_9.CE <= RW0_clk mem_0_9.A <= RW0_addr node RW0_rdata_0_9 = bits(mem_0_9.O, 0, 0) mem_0_9.I <= bits(RW0_wdata, 9, 9) - mem_0_9.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_9.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_9.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 9, 9)), UInt<1>("h1"))) mem_0_9.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_10.CE <= RW0_clk mem_0_10.A <= RW0_addr node RW0_rdata_0_10 = bits(mem_0_10.O, 0, 0) mem_0_10.I <= bits(RW0_wdata, 10, 10) - mem_0_10.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_10.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_10.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 10, 10)), UInt<1>("h1"))) mem_0_10.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_11.CE <= RW0_clk mem_0_11.A <= RW0_addr node RW0_rdata_0_11 = bits(mem_0_11.O, 0, 0) mem_0_11.I <= bits(RW0_wdata, 11, 11) - mem_0_11.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_11.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_11.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 11, 11)), UInt<1>("h1"))) mem_0_11.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_12.CE <= RW0_clk mem_0_12.A <= RW0_addr node RW0_rdata_0_12 = bits(mem_0_12.O, 0, 0) mem_0_12.I <= bits(RW0_wdata, 12, 12) - mem_0_12.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_12.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_12.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 12, 12)), UInt<1>("h1"))) mem_0_12.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_13.CE <= RW0_clk mem_0_13.A <= RW0_addr node RW0_rdata_0_13 = bits(mem_0_13.O, 0, 0) mem_0_13.I <= bits(RW0_wdata, 13, 13) - mem_0_13.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_13.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_13.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 13, 13)), UInt<1>("h1"))) mem_0_13.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_14.CE <= RW0_clk mem_0_14.A <= RW0_addr node RW0_rdata_0_14 = bits(mem_0_14.O, 0, 0) mem_0_14.I <= bits(RW0_wdata, 14, 14) - mem_0_14.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_14.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_14.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 14, 14)), UInt<1>("h1"))) mem_0_14.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_15.CE <= RW0_clk mem_0_15.A <= RW0_addr node RW0_rdata_0_15 = bits(mem_0_15.O, 0, 0) mem_0_15.I <= bits(RW0_wdata, 15, 15) - mem_0_15.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_15.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_15.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 15, 15)), UInt<1>("h1"))) mem_0_15.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_16.CE <= RW0_clk mem_0_16.A <= RW0_addr node RW0_rdata_0_16 = bits(mem_0_16.O, 0, 0) mem_0_16.I <= bits(RW0_wdata, 16, 16) - mem_0_16.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_16.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_16.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 16, 16)), UInt<1>("h1"))) mem_0_16.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_17.CE <= RW0_clk mem_0_17.A <= RW0_addr node RW0_rdata_0_17 = bits(mem_0_17.O, 0, 0) mem_0_17.I <= bits(RW0_wdata, 17, 17) - mem_0_17.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_17.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_17.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 17, 17)), UInt<1>("h1"))) mem_0_17.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_18.CE <= RW0_clk mem_0_18.A <= RW0_addr node RW0_rdata_0_18 = bits(mem_0_18.O, 0, 0) mem_0_18.I <= bits(RW0_wdata, 18, 18) - mem_0_18.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_18.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_18.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 18, 18)), UInt<1>("h1"))) mem_0_18.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_19.CE <= RW0_clk mem_0_19.A <= RW0_addr node RW0_rdata_0_19 = bits(mem_0_19.O, 0, 0) mem_0_19.I <= bits(RW0_wdata, 19, 19) - mem_0_19.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_19.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_19.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 19, 19)), UInt<1>("h1"))) mem_0_19.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_20.CE <= RW0_clk mem_0_20.A <= RW0_addr node RW0_rdata_0_20 = bits(mem_0_20.O, 0, 0) mem_0_20.I <= bits(RW0_wdata, 20, 20) - mem_0_20.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_20.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_20.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 20, 20)), UInt<1>("h1"))) mem_0_20.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_21.CE <= RW0_clk mem_0_21.A <= RW0_addr node RW0_rdata_0_21 = bits(mem_0_21.O, 0, 0) mem_0_21.I <= bits(RW0_wdata, 21, 21) - mem_0_21.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_21.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_21.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 21, 21)), UInt<1>("h1"))) mem_0_21.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_22.CE <= RW0_clk mem_0_22.A <= RW0_addr node RW0_rdata_0_22 = bits(mem_0_22.O, 0, 0) mem_0_22.I <= bits(RW0_wdata, 22, 22) - mem_0_22.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_22.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_22.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 22, 22)), UInt<1>("h1"))) mem_0_22.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_23.CE <= RW0_clk mem_0_23.A <= RW0_addr node RW0_rdata_0_23 = bits(mem_0_23.O, 0, 0) mem_0_23.I <= bits(RW0_wdata, 23, 23) - mem_0_23.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_23.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_23.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 23, 23)), UInt<1>("h1"))) mem_0_23.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_24.CE <= RW0_clk mem_0_24.A <= RW0_addr node RW0_rdata_0_24 = bits(mem_0_24.O, 0, 0) mem_0_24.I <= bits(RW0_wdata, 24, 24) - mem_0_24.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_24.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_24.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 24, 24)), UInt<1>("h1"))) mem_0_24.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_25.CE <= RW0_clk mem_0_25.A <= RW0_addr node RW0_rdata_0_25 = bits(mem_0_25.O, 0, 0) mem_0_25.I <= bits(RW0_wdata, 25, 25) - mem_0_25.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_25.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_25.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 25, 25)), UInt<1>("h1"))) mem_0_25.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_26.CE <= RW0_clk mem_0_26.A <= RW0_addr node RW0_rdata_0_26 = bits(mem_0_26.O, 0, 0) mem_0_26.I <= bits(RW0_wdata, 26, 26) - mem_0_26.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_26.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_26.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 26, 26)), UInt<1>("h1"))) mem_0_26.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_27.CE <= RW0_clk mem_0_27.A <= RW0_addr node RW0_rdata_0_27 = bits(mem_0_27.O, 0, 0) mem_0_27.I <= bits(RW0_wdata, 27, 27) - mem_0_27.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_27.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_27.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 27, 27)), UInt<1>("h1"))) mem_0_27.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_28.CE <= RW0_clk mem_0_28.A <= RW0_addr node RW0_rdata_0_28 = bits(mem_0_28.O, 0, 0) mem_0_28.I <= bits(RW0_wdata, 28, 28) - mem_0_28.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_28.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_28.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 28, 28)), UInt<1>("h1"))) mem_0_28.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_29.CE <= RW0_clk mem_0_29.A <= RW0_addr node RW0_rdata_0_29 = bits(mem_0_29.O, 0, 0) mem_0_29.I <= bits(RW0_wdata, 29, 29) - mem_0_29.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_29.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_29.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 29, 29)), UInt<1>("h1"))) mem_0_29.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_30.CE <= RW0_clk mem_0_30.A <= RW0_addr node RW0_rdata_0_30 = bits(mem_0_30.O, 0, 0) mem_0_30.I <= bits(RW0_wdata, 30, 30) - mem_0_30.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_30.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_30.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 30, 30)), UInt<1>("h1"))) mem_0_30.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_31.CE <= RW0_clk mem_0_31.A <= RW0_addr node RW0_rdata_0_31 = bits(mem_0_31.O, 0, 0) mem_0_31.I <= bits(RW0_wdata, 31, 31) - mem_0_31.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_31.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) diff --git a/macros/src/test/scala/SynFlops.scala b/macros/src/test/scala/SynFlops.scala index 8198d8f3..0723bb33 100644 --- a/macros/src/test/scala/SynFlops.scala +++ b/macros/src/test/scala/SynFlops.scala @@ -11,7 +11,7 @@ s""" mem_0_0.${libPortPrefix}_addr <= ${libPortPrefix}_addr node ${libPortPrefix}_dout_0_0 = bits(mem_0_0.${libPortPrefix}_dout, ${libWidth-1}, 0) mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth-1}, 0) - mem_0_0.${libPortPrefix}_write_en <= and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.${libPortPrefix}_write_en <= and(and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0 ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<1>("h0")) @@ -148,7 +148,7 @@ circuit target_memory : mem_0_0.innerB_clk <= outerA_clk mem_0_0.innerB_addr <= outerA_addr mem_0_0.innerB_din <= bits(outerA_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) + mem_0_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) mem_0_0.innerA_clk <= outerB_clk mem_0_0.innerA_addr <= outerB_addr node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) @@ -157,7 +157,7 @@ circuit target_memory : mem_1_0.innerB_clk <= outerA_clk mem_1_0.innerB_addr <= outerA_addr mem_1_0.innerB_din <= bits(outerA_din, 7, 0) - mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) + mem_1_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) mem_1_0.innerA_clk <= outerB_clk mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) @@ -182,7 +182,7 @@ circuit target_memory : mem_0_0.innerB_clk <= innerB_clk mem_0_0.innerB_addr <= innerB_addr mem_0_0.innerB_din <= bits(innerB_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.innerB_write_en <= and(and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_0.innerA_clk <= innerA_clk mem_0_0.innerA_addr <= innerA_addr node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) diff --git a/mdf b/mdf index 515dda51..4281e8f6 160000 --- a/mdf +++ b/mdf @@ -1 +1 @@ -Subproject commit 515dda51206eb40bcbe902700abc8ca36b141c0d +Subproject commit 4281e8f621decc10a8cdb878c593e46115c70998 diff --git a/tapeout/src/main/scala/transforms/ResetInverter.scala b/tapeout/src/main/scala/transforms/ResetInverter.scala index da090dbf..08d84983 100644 --- a/tapeout/src/main/scala/transforms/ResetInverter.scala +++ b/tapeout/src/main/scala/transforms/ResetInverter.scala @@ -34,11 +34,12 @@ object ResetN extends Pass { mod.copy(ports = portsx, body = bodyx) } - def run(c: Circuit): Circuit = + def run(c: Circuit): Circuit = { c.copy(modules = c.modules map { case mod: Module if mod.name == c.main => invertReset(mod) case other => other }) + } } class ResetInverterTransform extends Transform { diff --git a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala index 7abcbf4c..07fca302 100644 --- a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala +++ b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala @@ -22,7 +22,7 @@ class ResetNSpec extends FreeSpec with Matchers { "Inverting reset needs to be done throughout module" in { val optionsManager = new ExecutionOptionsManager("dsptools") with HasChiselExecutionOptions with HasFirrtlOptions { - firrtlOptions = firrtlOptions.copy(compilerName = "low") + firrtlOptions = firrtlOptions.copy(compilerName = "low", customTransforms = List(new ResetInverterTransform)), } chisel3.Driver.execute(optionsManager, () => new ExampleModuleNeedsResetInverted) match { case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) => diff --git a/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala b/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala index 7c634837..76223b71 100644 --- a/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala +++ b/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala @@ -27,10 +27,10 @@ class RetimeSpec extends FlatSpec with Matchers { val dir = uniqueDirName(gen, "RetimeModule") chisel3.Driver.execute(Array("-td", s"test_run_dir/$dir", "-foaf", s"test_run_dir/$dir/final"), gen) shouldBe a [ChiselExecutionSuccess] - val lines = io.Source.fromFile(s"test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n") + val lines = io.Source.fromFile(s"test_run_dir/$dir/test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n") lines should include("barstools.tapeout.transforms.retime.RetimeTransform") } - + // TODO(azidar): need to fix/add instance annotations ignore should "pass simple retime instance annotation" in { val gen = () => new RetimeInstance()