Add CanHaveClockTap

2023-12-15 13:23:47 -08:00
parent f882280290
commit d828879a7d
3 changed files with 30 additions and 0 deletions
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -86,6 +86,9 @@ case class CustomBootPort  (val getIO: () => Bool)
 case class ClockPort       (val getIO: () => Clock, val freqMHz: Double)
    extends Port[Clock]

+case class ClockTapPort    (val getIO: () => Clock)
+    extends Port[Clock]
+
 case class ResetPort       (val getIO: () => AsyncReset)
    extends Port[Reset]