diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index d7263008..7e73866c 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -33,6 +33,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
   with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
+  with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
 {
diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
new file mode 100644
index 00000000..798dfda8
--- /dev/null
+++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -0,0 +1,26 @@
+package chipyard.clocking
+
+import chisel3._
+
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.prci._
+
+case class ClockTapParams(
+  busWhere: TLBusWrapperLocation = SBUS, // by default, tap the sbus clock as a debug clock
+  divider: Int = 16, // a fixed clock division ratio for the clock tap
+)
+
+case object ClockTapKey extends Field[Option[ClockTapParams]](Some(ClockTapParams()))
+
+trait CanHaveClockTap { this: BaseSubsystem =>
+  val clockTapNode = p(ClockTapKey).map { tapParams =>
+    val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
+    val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
+    clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
+  }
+}
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
index c5c9f19e..867efdfd 100644
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -86,6 +86,9 @@ case class CustomBootPort  (val getIO: () => Bool)
 case class ClockPort       (val getIO: () => Clock, val freqMHz: Double)
     extends Port[Clock]
 
+case class ClockTapPort    (val getIO: () => Clock)
+    extends Port[Clock]
+
 case class ResetPort       (val getIO: () => AsyncReset)
     extends Port[Reset]