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Rename serialManagerParams -> serialTLManagerParams

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This commit is contained in:
Jerry Zhao
2023-05-13 19:25:14 -07:00
parent 3330c23193
commit d4d81f7d22
4 changed files with 14 additions and 14 deletions
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10
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
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@@ -40,9 +40,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// Serialized TL // Serialized TL
val sVal = p(SerialTLKey).get val sVal = p(SerialTLKey).get
val serialManagerParams = sVal.serialManagerParams.get val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialManagerParams.isMemoryDevice) require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(lazyDut.system) val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
withClockAndReset(clock, reset) { withClockAndReset(clock, reset) {
@@ -60,8 +60,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
val memSize = serialManagerParams.memParams.size val memSize = serialTLManagerParams.memParams.size
val memBase = serialManagerParams.memParams.base val memBase = serialTLManagerParams.memParams.base
val lineSize = p(CacheBlockBytes) val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits mem.io.axi <> axi_port.bits

10
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -145,9 +145,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
p(SerialTLKey).map({ sVal => p(SerialTLKey).map({ sVal =>
val serialManagerParams = sVal.serialManagerParams.get val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialManagerParams.isMemoryDevice) require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
@@ -168,8 +168,8 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
val memSize = serialManagerParams.memParams.size val memSize = serialTLManagerParams.memParams.size
val memBase = serialManagerParams.memParams.base val memBase = serialTLManagerParams.memParams.base
val lineSize = p(CacheBlockBytes) val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits mem.io.axi <> axi_port.bits

6
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -113,9 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
implicit val p = GetSystemParameters(system) implicit val p = GetSystemParameters(system)
p(SerialTLKey).map({ sVal => p(SerialTLKey).map({ sVal =>
val serialManagerParams = sVal.serialManagerParams.get val serialTLManagerParams = sVal.serialTLManagerParams.get
val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
require(serialManagerParams.isMemoryDevice) require(serialTLManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
ports.map({ port => ports.map({ port =>

2
generators/testchipip

Submodule generators/testchipip updated: 862a5db434...2e09aea4f1