From d4d81f7d220b4492f99827027e18250905f27cc9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 13 May 2023 19:25:14 -0700 Subject: [PATCH] Rename serialManagerParams -> serialTLManagerParams --- .../src/main/scala/example/FlatTestHarness.scala | 10 +++++----- .../src/main/scala/harness/HarnessBinders.scala | 10 +++++----- generators/firechip/src/main/scala/BridgeBinders.scala | 6 +++--- generators/testchipip | 2 +- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 6a62aa46..ee004dc1 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -40,9 +40,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // Serialized TL val sVal = p(SerialTLKey).get - val serialManagerParams = sVal.serialManagerParams.get - val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get - require(serialManagerParams.isMemoryDevice) + val serialTLManagerParams = sVal.serialTLManagerParams.get + val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get + require(serialTLManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(lazyDut.system) withClockAndReset(clock, reset) { @@ -60,8 +60,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => - val memSize = serialManagerParams.memParams.size - val memBase = serialManagerParams.memParams.base + val memSize = serialTLManagerParams.memParams.size + val memBase = serialTLManagerParams.memParams.base val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 7e97f5ff..bb6c4443 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -145,9 +145,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ implicit val p = chipyard.iobinders.GetSystemParameters(system) p(SerialTLKey).map({ sVal => - val serialManagerParams = sVal.serialManagerParams.get - val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get - require(serialManagerParams.isMemoryDevice) + val serialTLManagerParams = sVal.serialTLManagerParams.get + val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get + require(serialTLManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) @@ -168,8 +168,8 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => - val memSize = serialManagerParams.memParams.size - val memBase = serialManagerParams.memParams.base + val memSize = serialTLManagerParams.memParams.size + val memBase = serialTLManagerParams.memParams.base val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 0def2e38..a93fea89 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -113,9 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ implicit val p = GetSystemParameters(system) p(SerialTLKey).map({ sVal => - val serialManagerParams = sVal.serialManagerParams.get - val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get - require(serialManagerParams.isMemoryDevice) + val serialTLManagerParams = sVal.serialTLManagerParams.get + val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get + require(serialTLManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) ports.map({ port => diff --git a/generators/testchipip b/generators/testchipip index 862a5db4..2e09aea4 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 862a5db434d67eb6c4482b2e8bfa81381d9c6314 +Subproject commit 2e09aea4f1dd630ff2ed33e531e8c9a006d55779