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Update project-template for testchipip master

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This commit is contained in:
Edward Wang
2018-11-01 14:13:38 -07:00
committed by edwardcwang
parent cd82131748
commit d48587b671
3 changed files with 4 additions and 3 deletions
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2
Makefrag
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@@ -25,7 +25,7 @@ include $(testchip_dir)/Makefrag
CHISEL_ARGS ?= CHISEL_ARGS ?=
FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json
VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR) $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)

3
src/main/scala/example/TestHarness.scala
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@@ -3,7 +3,7 @@ package example
import chisel3._ import chisel3._
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import testchipip.GeneratorApp import freechips.rocketchip.util.GeneratorApp
case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]] case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
@@ -21,6 +21,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
} }
object Generator extends GeneratorApp { object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl generateFirrtl
generateAnno generateAnno
} }

2
testchipip

Submodule testchipip updated: 5aebd3a48d...208daac5bd