wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Update scratchpad config (#371)

Browse Source 
* Update scratchpad config

Previous version didn't compile as per
https://github.com/ucb-bar/chipyard/issues/365

* Update docs/Customization/Memory-Hierarchy.rst

Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>

* Fix indentation

* Update memory hierarchy doc for PR

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
This commit is contained in:
Baltazar Ortiz
2020-01-10 11:02:21 -08:00
committed by Abraham Gonzalez
parent f60e1a9c89
commit d277984eab
1 changed files with 23 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
docs/Customization/Memory-Hierarchy.rst
View File

@@ -9,19 +9,23 @@ The L1 Caches
Each CPU tile has an L1 instruction cache and L1 data cache. The size and
associativity of these caches can be configured. The default ``RocketConfig``
uses 16 KiB, 4-way set-associative instruction and data caches. However,
if you use the ``NMediumCores`` or ``NSmallCores`` configurations, you can
if you use the ``NMedCores`` or ``NSmallCores`` configurations, you can
configure 4 KiB direct-mapped caches for L1I and L1D.
.. code-block:: scala
import freechips.rocketchip.subsystem.{WithNMediumCores, WithNSmallCores}
class SmallRocketConfig extends Config(
new WithTop ++ // use default top
new WithBootROM ++ // use default bootrom
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class SmallRocketConfig extends Config(
new WithNSmallCores(1) ++
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
new RocketConfig)
class MediumRocketConfig extends Config(
new WithNMediumCores(1) ++
new freechips.rocketchip.subsystem.WithNMedCores(1) ++
new RocketConfig)
If you only want to change the size or associativity, there are configuration
@@ -41,15 +45,25 @@ mixins for those too.
You can also configure the L1 data cache as an data scratchpad instead.
However, there are some limitations on this. If you are using a data scratchpad,
you can only use a single core and you cannot give the design an external DRAM.
Note that these configurations fully remove the L2 cache and mbus.
.. code-block:: scala
import freechips.rocketchip.subsystem.{WithNoMemPort, WithScratchpadsOnly}
class SmallRocketConfigNoL2 extends Config(
new WithTop ++ // use default top
new WithBootROM ++ // use default bootrom
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class ScratchpadRocketConfig extends Config(
new WithNoMemPort ++
new WithScratchpadsOnly ++
new SmallRocketConfig)
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++
new SmallRocketConfigNoL2)
This configuration fully removes the L2 cache and memory bus by setting the
number of channels and number of banks to 0.
The SiFive L2 Cache
-------------------