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Merge pull request #269 from ucb-bar/fased-config-fixes

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Move FASED Configs into TARGET_CONFIG strings
This commit is contained in:
David Biancolin
2019-10-05 14:17:08 -07:00
committed by GitHub
parent 0f4009d401 370c0dbfa8
commit d103ef1e93
5 changed files with 15 additions and 52 deletions
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6
.circleci/defaults.sh
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@@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig"
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"

42
generators/firechip/src/main/scala/SimConfigs.scala
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@@ -1,42 +0,0 @@
//See LICENSE for license details.
package firesim.firesim
import freechips.rocketchip.config.{Parameters, Config, Field}
import midas.models._
import firesim.endpoints._
import firesim.configs._
/*******************************************************************************
* Full PLATFORM_CONFIG Configurations. These set simulator parameters.
*
* In general, if you're adding or removing features from any of these, you
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
* will store this name as part of the tags for the AGFI, so that later you can
* reconstruct what is in a particular AGFI. These tags are also used to
* determine which driver to build.
*******************************************************************************/
class FireSimConfig extends Config(new BasePlatformConfig)
class FireSimClockDivConfig extends Config(
new FireSimConfig)
class FireSimDDR3Config extends Config(
new FireSimConfig)
class FireSimDDR3LLC4MBConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSLLC4MBConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
new FireSimConfig)
class Midas2Config extends Config(
new WithMultiCycleRamModels ++
new FireSimConfig)

7
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -20,7 +20,7 @@ import icenet._
import firesim.endpoints._
import firesim.util.{WithNumNodes}
import firesim.configs.WithDefaultMemModel
import firesim.configs._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => {
@@ -86,6 +86,11 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
case PrintTracePort => true
})
// FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div
/*******************************************************************************
* Full TARGET_CONFIG configurations. These set parameters of the target being
* simulated.

10
generators/firechip/src/test/scala/ScalaTestSuite.scala
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@@ -130,10 +130,10 @@ abstract class FireSimTestSuite(
runSuite("verilator")(FastBlockdevTests)
}
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
runSuite("verilator")(NICLoopbackTests)
}
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")

2
sims/firesim

Submodule sims/firesim updated: 26ffba7cbc...31682ca995