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Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main

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This commit is contained in:
Richard Yan
2024-04-20 02:03:35 -07:00
parent e75c77a08a bd664d5156
commit d0b274ab78
91 changed files with 2109 additions and 1555 deletions
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2
generators/boom

Submodule generators/boom updated: 9459af0c1f...506c11c99c

12
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -19,9 +19,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
@@ -43,12 +45,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l)
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop

10
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -20,9 +20,6 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
@@ -92,7 +89,8 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
{
def coreMonitorBundles = totalTiles.values.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
case b: boom.v3.common.BoomTile => b.module.core.coreMonitorBundle
case b: boom.v4.common.BoomTile => b.module.core.coreMonitorBundle
}.toList
// No-tile configs have to be handled specially.
@@ -132,6 +130,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
}
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasHierarchicalElementsRootContextModuleImp
{
with HasHierarchicalElementsRootContextModuleImp {
override lazy val outer = _outer
}

19
generators/chipyard/src/main/scala/System.scala
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@@ -38,7 +38,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
/**
* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with DontTouch
@@ -60,6 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
private val portName = "tl_mem"
private val device = new MemoryDevice
private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS))
val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
Seq.tabulate(nMemoryChannels) { channel =>
@@ -76,15 +77,15 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
supportsPutFull = TransferSizes(1, mbus.blockBytes),
supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
beatBytes = memPortParams.beatBytes)
}
}).toList.flatten)
}
}).toList.flatten)
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)
mbus.coupleTo(s"memory_controller_port_named_$portName") {
(memTLNode
:*= TLBuffer()
:*= TLSourceShrinker(1 << idBits)
:*= TLWidthWidget(mbus.beatBytes)
:*= _)
}
val mem_tl = InModuleBody { memTLNode.makeIOs() }

165
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -11,24 +11,32 @@ import org.chipsalliance.cde.config.{Config}
// --------------
class AbstractConfig extends Config(
// ================================================
// Set up TestHarness
// ================================================
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed
new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present
new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port
new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */
new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */
new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */
new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */
new chipyard.harness.WithGPIOPinsTiedOff ++ /** tie-off chiptop GPIO-pins, if GPIO-punchthrough is used */
new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */
new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */
new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */
new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */
new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */
new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
new chipyard.harness.WithDriveChipIdPin ++ /** drive chip id pin from harness binder, if chip id pin is present */
new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */
new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
// ================================================
// Set up I/O cells + punch I/Os in ChipTop
// ================================================
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
// IOCells are generated for "Chip-like" IOs
new chipyard.iobinders.WithSerialTLIOCells ++
@@ -53,42 +61,99 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++
new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
// ================================================
// Set up External Memory and IO Devices
// ================================================
// External memory section
new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
)
)) ++
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
// MMIO device section
new chipyard.config.WithUART ++ /** add a UART */
// ================================================
// Set up Debug/Bringup/Testing Features
// ================================================
// JTAG
new freechips.rocketchip.subsystem.WithDebugSBA ++ /** enable the SBA (system-bus-access) feature of the debug module */
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */
new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
// Boot Select Pins
new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
// ================================================
// Set up Interrupts
// ================================================
// CLINT and PLIC related settings goes here
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */
// ================================================
// Set up Tiles
// ================================================
// tile-local settings goes here
// ================================================
// Set up Memory system
// ================================================
// On-chip memory section
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
new chipyard.config.WithBootROM ++ /** use default bootrom */
new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */
size = 64 * 1024) ++
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// Coherency settings
new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence */
// Bus/interconnect settings
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */
// ================================================
// Set up power, reset and clocking
// ================================================
// ChipTop clock IO/PLL/Divider/Mux settings
new chipyard.clocking.WithClockTapIOCells ++ /** Default generate a clock tapio */
new chipyard.clocking.WithPassthroughClockGenerator ++
// DigitalTop-internal clocking settings
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */
new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */
new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */
new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */
new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */
new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */
new chipyard.config.WithNoSubsystemClockIO ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
// reset
// power
// ==================================
// Base Settings
// ==================================
new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */
)

100
generators/chipyard/src/main/scala/config/BoomConfigs.scala
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@@ -3,60 +3,116 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
// ---------------------
// BOOM Configs
// BOOM V3 Configs
// Performant, stable baseline
// ---------------------
class SmallBoomConfig extends Config(
new boom.common.WithNSmallBooms(1) ++ // small boom config
class SmallBoomV3Config extends Config(
new boom.v3.common.WithNSmallBooms(1) ++ // small boom config
new chipyard.config.AbstractConfig)
class MediumBoomConfig extends Config(
new boom.common.WithNMediumBooms(1) ++ // medium boom config
class MediumBoomV3Config extends Config(
new boom.v3.common.WithNMediumBooms(1) ++ // medium boom config
new chipyard.config.AbstractConfig)
class LargeBoomConfig extends Config(
new boom.common.WithNLargeBooms(1) ++ // large boom config
class LargeBoomV3Config extends Config(
new boom.v3.common.WithNLargeBooms(1) ++ // large boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MegaBoomConfig extends Config(
new boom.common.WithNMegaBooms(1) ++ // mega boom config
class MegaBoomV3Config extends Config(
new boom.v3.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DualSmallBoomConfig extends Config(
new boom.common.WithNSmallBooms(2) ++ // 2 boom cores
class DualSmallBoomV3Config extends Config(
new boom.v3.common.WithNSmallBooms(2) ++ // 2 boom cores
new chipyard.config.AbstractConfig)
class Cloned64MegaBoomConfig extends Config(
new boom.common.WithCloneBoomTiles(63, 0) ++
new boom.common.WithNMegaBooms(1) ++ // mega boom config
class Cloned64MegaBoomV3Config extends Config(
new boom.v3.common.WithCloneBoomTiles(63, 0) ++
new boom.v3.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class LoopbackNICLargeBoomConfig extends Config(
class LoopbackNICLargeBoomV3Config extends Config(
new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback
new icenet.WithIceNIC ++ // build a NIC
new boom.common.WithNLargeBooms(1) ++
new boom.v3.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
class MediumBoomV3CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomConfig extends Config(
class dmiMediumBoomV3Config extends Config(
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomCosimConfig extends Config(
class dmiMediumBoomV3CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.common.WithNMediumBooms(1) ++
new boom.v3.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
// ---------------------
// BOOM V4 Configs
// Less stable and performant, but with more advanced micro-architecture
// Use for PD exploration
// ---------------------
class SmallBoomV4Config extends Config(
new boom.v4.common.WithNSmallBooms(1) ++ // small boom config
new chipyard.config.AbstractConfig)
class MediumBoomV4Config extends Config(
new boom.v4.common.WithNMediumBooms(1) ++ // medium boom config
new chipyard.config.AbstractConfig)
class LargeBoomV4Config extends Config(
new boom.v4.common.WithNLargeBooms(1) ++ // large boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MegaBoomV4Config extends Config(
new boom.v4.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class DualSmallBoomV4Config extends Config(
new boom.v4.common.WithNSmallBooms(2) ++ // 2 boom cores
new chipyard.config.AbstractConfig)
class Cloned64MegaBoomV4Config extends Config(
new boom.v4.common.WithCloneBoomTiles(63, 0) ++
new boom.v4.common.WithNMegaBooms(1) ++ // mega boom config
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomV4CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomV4Config extends Config(
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)
class dmiMediumBoomV4CosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new boom.v4.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)

6
generators/chipyard/src/main/scala/config/ChipConfigs.scala
View File

@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
isMemoryDevice = true
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock
))) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port
@@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config(
size = BigInt("80000000", 16)
))
)),
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock
client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM)
phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
))) ++
//============================

50
generators/chipyard/src/main/scala/config/ChipletConfigs.scala
View File

@@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga
client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client
phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock
),
testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client
@@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config(
)),
slaveWhere = OBUS
)),
phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
))
) ++
new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory
@@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config(
new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
)
// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
class RocketCoreChipletConfig extends Config(
new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams()),
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
),
testchipip.serdes.SerialTLParams(
manager = Some(testchipip.serdes.SerialTLManagerParams(
cohParams = Seq(testchipip.serdes.ManagerCOHParams(
address = BigInt("80000000", 16),
size = BigInt("100000000", 16)
)),
slaveWhere = OBUS,
isMemoryDevice = true
)),
phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
)
)) ++
new testchipip.soc.WithOffchipBusClient(SBUS) ++
new testchipip.soc.WithOffchipBus ++
new testchipip.soc.WithNoScratchpads ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// LLC-only chiplet
class LLCChipletConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip
client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd
))) ++
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
new chipyard.NoCoresConfig
)
class MultiSimLLCChipletRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++
new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++
new chipyard.harness.WithMultiChip(1, new LLCChipletConfig)
)

14
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
// ---------------------
class LargeBoomAndRocketConfig extends Config(
new boom.common.WithNLargeBooms(1) ++ // single-core boom
new boom.v3.common.WithNLargeBooms(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -16,7 +16,7 @@ class LargeBoomAndRocketConfig extends Config(
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -26,7 +26,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.common.WithNLargeBooms(1) ++ // add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -36,21 +36,21 @@ class DualLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket)
new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: DualBoomAndRocketOneHwacha
class DualLargeBoomAndDualRocketConfig extends Config(
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: DualBoomAndSingleRocket
class DualLargeBoomAndSingleRocketConfig extends Config(
new boom.common.WithNLargeBooms(2) ++ // add 2 boom cores
new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
@@ -58,7 +58,7 @@ class DualLargeBoomAndSingleRocketConfig extends Config(
class LargeBoomAndRocketWithControlCoreConfig extends Config(
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
new boom.common.WithNLargeBooms(1) ++ // Add 1 boom core
new boom.v3.common.WithNLargeBooms(1) ++ // Add 1 boom core
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)

1
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
View File

@@ -59,6 +59,7 @@ class LargeNVDLARocketConfig extends Config(
new chipyard.config.AbstractConfig)
class ManyMMIOAcceleratorRocketConfig extends Config(
new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO: hack around dontTouch not working in SFC
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough

10
generators/chipyard/src/main/scala/config/NoCConfigs.scala
View File

@@ -240,7 +240,7 @@ class SbusMeshNoCConfig extends Config(
"Core 9 " -> 13,
"Core 10 " -> 14,
"Core 11 " -> 15,
"serial-tl" -> 0),
"serial_tl" -> 0),
outNodeMapping = ListMap(
"system[0]" -> 5,
"system[1]" -> 6,
@@ -251,14 +251,16 @@ class SbusMeshNoCConfig extends Config(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1),
),
beNoCParams = NoCParams(
topology = Mesh2D(4, 4),
channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1),
),
beDivision = 4
)) ++
), inlineNoC = true) ++
new freechips.rocketchip.subsystem.WithNBigCores(12) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++

1
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config(
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithPeripheryTimer ++ // add the pwm timer device
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port

4
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
View File

@@ -50,10 +50,10 @@ class MempressRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class HwachaLargeBoomConfig extends Config(
class HwachaLargeBoomV3Config extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new boom.common.WithNLargeBooms(1) ++
new boom.v3.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)

9
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
View File

@@ -18,7 +18,8 @@ class dmiSpikeConfig extends Config(
// Avoids polling on the UART registers
class SpikeFastUARTConfig extends Config(
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.AbstractConfig)
@@ -27,7 +28,8 @@ class SpikeFastUARTConfig extends Config(
class SpikeUltraFastConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++
@@ -47,7 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++

9
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -32,8 +32,13 @@ class NonBlockingTraceGenConfig extends Config(
new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new AbstractTraceGenConfig)
class BoomTraceGenConfig extends Config(
new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
class BoomV3TraceGenConfig extends Config(
new tracegen.WithBoomV3TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)
class BoomV4TraceGenConfig extends Config(
new tracegen.WithBoomV4TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new AbstractTraceGenConfig)

2
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -32,7 +32,7 @@ class TutorialStarterConfig extends Config(
// Uncomment out one (or multiple) of the lines below, and choose
// how many cores you want.
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
// new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
// new boom.v3.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
// CUSTOMIZE the L2
// Uncomment this line, and specify a size if you want to have a L2

10
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
View File

@@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.timer._
import testchipip._
@@ -65,11 +66,12 @@ class WithNoUART extends Config((site, here, up) => {
* @param address the address of the UART device
* @param baudrate the baudrate of the UART device
*/
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => {
class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000, txEntries: Int = 8, rxEntries: Int = 8) extends Config ((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq(
UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
UARTParams(address = address, nTxEntries = txEntries, nRxEntries = rxEntries, initBaudRate = baudrate))
})
// @deprecated("Use WithUART instead of WithUARTFIFOEntries", "chipyard v1.10")
class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
})
@@ -168,3 +170,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => {
case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
})
class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => {
case PeripheryTimerKey => Seq(timerParams)
})

46
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -5,9 +5,8 @@ import chisel3._
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, PgLevels}
import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import sodor.common.{SodorTileAttachParams}
import ibex.{IbexTileAttachParams}
@@ -18,7 +17,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case other => other
}
@@ -26,7 +27,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
class WithTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = true)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = true)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
@@ -37,7 +40,9 @@ class WithTraceIO extends Config((site, here, up) => {
class WithNoTraceIO extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = false)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(trace = false)))
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = false))
@@ -50,7 +55,9 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case other => other
}
@@ -60,7 +67,9 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPMPs = n)))
case other => other
}
@@ -95,7 +104,9 @@ class WithTilePrefetchers extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
@@ -108,10 +119,15 @@ class WithTilePrefetchers extends Config((site, here, up) => {
// Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
// This typically makes it easier to close timing
class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
boundaryBuffers=buffers
))
}
})
class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
boundaryBuffers=buffers
))
}
})
// Uses SV48 if possible, otherwise default to the Rocket Chip core default
class WithSV48IfPossible extends Config((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
})

4
generators/chipyard/src/main/scala/example/CustomChipTop.scala
View File

@@ -67,13 +67,13 @@ class WithCustomChipTop extends Config((site, here, up) => {
})
class WithBrokenOutUARTIO extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
(system: HasPeripheryUART) => {
val uart_txd = IO(Output(Bool()))
val uart_rxd = IO(Input(Bool()))
system.uart(0).rxd := uart_rxd
uart_txd := system.uart(0).txd
val where = PBUS // TODO fix
val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(Seq(UARTPort(() => {
val uart_wire = Wire(new UARTPortIO(system.uart(0).c))

2
generators/chipyard/src/main/scala/example/FlatChipTop.scala
View File

@@ -145,7 +145,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
// UART
//==========================
require(system.uarts.size == 1)
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.uart.head, "uart_0", p(IOCellKey))
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000

10
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
View File

@@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// Figure out which clock drives the harness TLSerdes, based on the port type
val serial_ram_clock = dut.serial_tl_pad match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => clock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => clock
}
dut.serial_tl_pad match {
case io: ExternalSyncSerialIO => io.clock_in := clock
case io: InternalSyncSerialIO =>
case io: ExternalSyncPhitIO => io.clock_in := clock
case io: InternalSyncPhitIO =>
}
dut.serial_tl_pad match {
case pad: DecoupledSerialIO => {
case pad: DecoupledPhitIO => {
withClockAndReset(serial_ram_clock, reset) {
// SerialRAM implements the memory regions the chip expects
val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)

4
generators/chipyard/src/main/scala/example/GCD.scala
View File

@@ -5,7 +5,7 @@ import chisel3.util._
import chisel3.experimental.{IntParam, BaseModule}
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -194,6 +194,8 @@ class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends
trait CanHavePeripheryGCD { this: BaseSubsystem =>
private val portName = "gcd"
private val pbus = locateTLBusWrapper(PBUS)
// Only build if we are using the TL (nonAXI4) version
val gcd_busy = p(GCDKey) match {
case Some(params) => {

5
generators/chipyard/src/main/scala/example/InitZero.scala
View File

@@ -2,7 +2,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import freechips.rocketchip.tilelink._
@@ -61,7 +61,8 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
implicit val p: Parameters
p(InitZeroKey) .map { k =>
val initZero = LazyModule(new InitZero()(p))
val fbus = locateTLBusWrapper(FBUS)
val initZero = fbus { LazyModule(new InitZero()(p)) }
fbus.coupleFrom("init-zero") { _ := initZero.node }
}
}

1
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
View File

@@ -199,6 +199,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match {
case Some(params) => {
val pbus = locateTLBusWrapper(PBUS)
val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP),

1
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
View File

@@ -131,6 +131,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
val pbus = locateTLBusWrapper(PBUS)
val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }

29
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -44,6 +44,14 @@ class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
class WithGPIOTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
port.io <> AnalogConst(0)
}
})
class WithGPIOPinsTiedOff extends HarnessBinder({
case (th: HasHarnessInstantiators, port: GPIOPinsPort, chipId: Int) => {
port.io := DontCare
}
})
@@ -209,17 +217,17 @@ class WithTiedOffDMI extends HarnessBinder({
class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
port.io match {
case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncSerialIO => {
case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
case io: SourceSyncPhitIO => {
io.clock_in := false.B.asClock
io.reset_in := false.B.asAsyncReset
io.in := DontCare
io.credit_in := DontCare
}
}
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
case io: SourceSyncPhitIO =>
case _ =>
}
}
@@ -228,17 +236,18 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
class WithSimTSIOverSerialTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
port.io match {
case io: InternalSyncSerialIO =>
case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
case io: InternalSyncPhitIO =>
case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
}
port.io match {
case io: DecoupledSerialIO => {
case io: DecoupledPhitIO => {
// If the port is locally synchronous (provides a clock), drive everything with that clock
// Else, drive everything with the harnes clock
val clock = port.io match {
case io: InternalSyncSerialIO => io.clock_out
case io: ExternalSyncSerialIO => th.harnessBinderClock
case io: InternalSyncPhitIO => io.clock_out
case io: ExternalSyncPhitIO => th.harnessBinderClock
}
withClock(clock) {
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)

12
generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
View File

@@ -59,25 +59,23 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
(p0: SerialTLPort) => p0.portId == chip0portId,
(p1: SerialTLPort) => p1.portId == chip1portId,
(th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = {
clkSink.clock_in := clkSource.clock_out
clkSink.in <> clkSource.out
clkSource.in <> clkSink.out
}
def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = {
a.clock_in := b.clock_out
b.clock_in := a.clock_out
a.reset_in := b.reset_out
b.reset_in := a.reset_out
a.in := b.out
b.in := a.out
a.credit_in := b.credit_out
b.credit_in := a.credit_out
}
(p0.io, p1.io) match {
case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1)
case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1)
}
}
)

41
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View File

@@ -5,7 +5,12 @@ import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
@@ -165,15 +170,17 @@ case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
@@ -183,7 +190,7 @@ class WithGPIOCells extends OverrideIOBinder({
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
@@ -194,7 +201,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2CModuleImp) => {
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
@@ -206,11 +213,12 @@ class WithI2CPunchthrough extends OverrideIOBinder({
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
@@ -226,7 +234,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
@@ -238,20 +246,20 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp) => {
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset)
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
@@ -260,7 +268,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({
iocell
}
(SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
@@ -418,7 +426,8 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode)
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {

2
generators/chipyard/src/main/scala/iobinders/Ports.scala
View File

@@ -16,8 +16,8 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
import freechips.rocketchip.devices.debug.{ClockedDMIIO}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
trait Port[T <: Data] {
val getIO: () => T

2
generators/constellation

Submodule generators/constellation updated: 81f005ffea...6664839b10

1
generators/diplomacy Submodule

Submodule generators/diplomacy added at edf375300d

2
generators/fft-generator

Submodule generators/fft-generator updated: 4e7e6cbbbc...490b975d36

4
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import sifive.blocks.devices.uart._
import testchipip.serdes.{ExternalSyncSerialIO}
import testchipip.serdes.{ExternalSyncPhitIO}
import testchipip.tsi.{SerialRAM}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
case (th: FireSim, port: SerialTLPort, chipId: Int) => {
port.io match {
case io: ExternalSyncSerialIO => {
case io: ExternalSyncPhitIO => {
io.clock_in := th.harnessBinderClock
val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
ram.io.ser.in <> io.out

6
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
import freechips.rocketchip.tile.{RocketTile}
import boom.common.{BoomTile}
import boom.v3.common.{BoomTile}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
@@ -112,10 +112,10 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
case b: BoomTile => {
val core = b.module.core
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case irf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case frf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
}
}
case _ =>

26
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -107,7 +107,10 @@ class WithFireSimDesignTweaks extends Config(
// Optional: reduce the width of the Serial TL interface
new testchipip.serdes.WithSerialTLWidth(4) ++
// Required*: Scale default baud rate with periphery bus frequency
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new chipyard.config.WithUART(
baudrate=BigInt(3686400L),
txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
// Optional: Adds IO to attach tracerV bridges
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
@@ -201,7 +204,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new WithFireSimDesignTweaks
)
@@ -264,8 +267,8 @@ class FireSimSmallSystemConfig extends Config(
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits = 4)),
phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32)
))) ++
new testchipip.iceblk.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
@@ -273,13 +276,13 @@ class FireSimSmallSystemConfig extends Config(
new chipyard.RocketConfig)
//*****************************************************************
// Boom config, base off chipyard's LargeBoomConfig
// Boom config, base off chipyard's LargeBoomV3Config
//*****************************************************************
class FireSimLargeBoomConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomConfig)
new chipyard.LargeBoomV3Config)
//********************************************************************
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
@@ -335,11 +338,11 @@ class FireSimCVA6Config extends Config(
// - Requires MTModels and MCRams mixins as prefixes to the platform config
// - May require larger build instances or JVM memory footprints
//*********************************************************************************/
class FireSim16LargeBoomConfig extends Config(
class FireSim16LargeBoomV3Config extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new boom.common.WithNLargeBooms(16) ++
new boom.v3.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)
class FireSimNoMemPortConfig extends Config(
@@ -360,3 +363,10 @@ class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config(
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LeanGemminiRocketConfig)
class FireSimLargeBoomCospikeConfig extends Config(
new firesim.firesim.WithCospikeBridge ++
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks++
new chipyard.LargeBoomV3Config)

2
generators/mempress

Submodule generators/mempress updated: c3d4901ab0...415f55b583

2
generators/nvdla

Submodule generators/nvdla updated: 95697452e5...cfcb5fafcb

2
generators/rocc-acc-utils

Submodule generators/rocc-acc-utils updated: b001c888f9...9b8c5d375f

2
generators/rocket-chip-blocks

Submodule generators/rocket-chip-blocks updated: 3dddfe9f5b...2fc961f356

2
generators/sha3

Submodule generators/sha3 updated: 5e49347f06...2d38585d64

2
generators/shuttle

Submodule generators/shuttle updated: fd325d43a1...b75fada257

43
generators/tracegen/src/main/scala/Configs.scala
View File

@@ -8,7 +8,6 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.BaseConfig
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
import boom.lsu._
import scala.math.{max, min}
class WithTraceGen(
@@ -50,7 +49,7 @@ class WithTraceGen(
case NumTiles => up(NumTiles) + n
})
class WithBoomTraceGen(
class WithBoomV3TraceGen(
n: Int = 2,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
@@ -61,8 +60,44 @@ class WithBoomTraceGen(
val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
BoomTraceGenTileAttachParams(
tileParams = BoomTraceGenParams(
boom.v3.lsu.BoomTraceGenTileAttachParams(
tileParams = boom.v3.lsu.BoomTraceGenParams(
tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val nSets = dcp.nSets
val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = site(SystemBusKey).blockBeats
List.tabulate(nWays) { i =>
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
}.flatten
},
maxRequests = nReqs,
memStart = memOffset,
numGens = params.size),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
case NumTiles => up(NumTiles) + n
})
class WithBoomV4TraceGen(
n: Int = 2,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
boom.v4.lsu.BoomTraceGenTileAttachParams(
tileParams = boom.v4.lsu.BoomTraceGenParams(
tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),

6
generators/tracegen/src/main/scala/System.scala
View File

@@ -6,7 +6,6 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with InstantiatesHierarchicalElements
@@ -20,10 +19,11 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
val tileStatusNodes = totalTiles.values.toSeq.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
case t: boom.v3.lsu.BoomTraceGenTile => t.statusNode.makeSink()
case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
}
lazy val fakeClockDomain = sbus.generateSynchronousDomain
lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain
lazy val clintOpt = None
lazy val debugOpt = None