wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Typo

Browse Source
This commit is contained in:
Edward Wang
2017-03-15 00:28:30 -07:00
parent f7056f3529
commit d039935642
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala
View File

@@ -7,7 +7,7 @@ import firrtl.ir._
import firrtl.passes.Pass import firrtl.passes.Pass
// This doesn't rename ExtModules under the assumption that they're some // This doesn't rename ExtModules under the assumption that they're some
// Verilog black box and therefor can't be renamed. Since the point is to // Verilog black box and therefore can't be renamed. Since the point is to
// allow FIRRTL to be linked together using "cat" and ExtModules don't get // allow FIRRTL to be linked together using "cat" and ExtModules don't get
// emitted, this should be safe. // emitted, this should be safe.
class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass { class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass {