From d039935642f4537aebe70de4a6b305cb9484480c Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Wed, 15 Mar 2017 00:28:30 -0700 Subject: [PATCH] Typo --- .../src/main/scala/transforms/RenameModulesAndInstances.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala b/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala index 6adeacf0..f0a4dd80 100644 --- a/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala +++ b/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala @@ -7,7 +7,7 @@ import firrtl.ir._ import firrtl.passes.Pass // This doesn't rename ExtModules under the assumption that they're some -// Verilog black box and therefor can't be renamed. Since the point is to +// Verilog black box and therefore can't be renamed. Since the point is to // allow FIRRTL to be linked together using "cat" and ExtModules don't get // emitted, this should be safe. class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass {