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[clocks] Fix comment in ClockDividerN

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This commit is contained in:
David Biancolin
2020-09-17 11:32:51 -07:00
parent b8d3e4a66d
commit cfa7e30d95
1 changed files with 1 additions and 1 deletions
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generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv
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@@ -2,7 +2,7 @@
/** /**
* An unsynthesizable divide-by-N clock divider. * An unsynthesizable divide-by-N clock divider.
* Duty cycle is 100 * (ceil(DIV / 2)) / 2. * Duty cycle is 100 * (ceil(DIV / 2)) / DIV.
*/ */
module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in); module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in);