From cfa7e30d95f82acc69811753183ca6b681f8954a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 17 Sep 2020 11:32:51 -0700 Subject: [PATCH] [clocks] Fix comment in ClockDividerN --- generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv index 33f7a05b..868b0eee 100644 --- a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv +++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv @@ -2,7 +2,7 @@ /** * An unsynthesizable divide-by-N clock divider. - * Duty cycle is 100 * (ceil(DIV / 2)) / 2. + * Duty cycle is 100 * (ceil(DIV / 2)) / DIV. */ module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in);