Attempt at checking for Fixed types
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@@ -0,0 +1,72 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms
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import firrtl._
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import firrtl.annotations.{ModuleTarget, ReferenceTarget, SingleTargetAnnotation}
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import firrtl.ir._
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import firrtl.options.Dependency
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import firrtl.passes.memlib.ReplSeqMem
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import firrtl.stage.Forms
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import firrtl.stage.{RunFirrtlTransformAnnotation}
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import firrtl.stage.TransformManager.TransformDependency
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class CheckForUnsupportedFirtoolTypes extends Transform with DependencyAPIMigration {
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override def prerequisites: Seq[TransformDependency] = Forms.ChirrtlForm
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override def optionalPrerequisites: Seq[TransformDependency] = Seq.empty
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override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq.empty
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override def invalidates(a: Transform): Boolean = false
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def run(state: CircuitState): Boolean = {
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val c = state.circuit
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//def checkFixed(t: Type): Unit = {
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// println(s"checkFixed -> $t")
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// t match {
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// case FixedType(_, _) => {
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// runLowering = true
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// println(s"runLowering is $runLowering")
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// }
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// case _ => Unit
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// }
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//}
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def onStmtType(s: Statement): Boolean = {
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var runLowering = false
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println(s"Entering onStmtType")
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def recursive(s: Statement): Unit = {
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s match {
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case x: DefRegister => x.foreachType(_ => println(s"It works!"))
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case x: DefWire => x.foreachType(_ => println(s"1 It works!"))
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case x: DefNode => x.foreachType(_ => println(s"2 It works!"))
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case x: DefMemory => x.foreachType(_ => println(s"3 It works!"))
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case x: WDefInstance => x.foreachType(_ => println(s"4 It works!"))
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case x: Connect => x.foreachType(_ => println(s"5 It works!"))
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case x: PartialConnect => x.foreachType(_ => println(s"6 It works!"))
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case x: Block => x.foreachStmt(recursive)
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case x => x.foreachType(_ => println(s"Uh oh"))
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}
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}
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//s.foreachType(checkFixed)
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s.foreachType(_ => println("Reached"))
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runLowering
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}
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val runLoweringOverall = c.modules.map {
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case m: ExtModule => false
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case m: Module => onStmtType(m.body)
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}
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runLoweringOverall.reduce(_ || _)
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}
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def execute(state: CircuitState): CircuitState = {
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val runLoweringAnnos = Seq(RunFirrtlTransformAnnotation(new MiddleFirrtlEmitter))
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val doLowering = run(state)
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println(s"DEBUG: Final doLowering -> $doLowering")
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state.copy(annotations = state.annotations)
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}
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}
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@@ -7,13 +7,13 @@ import firrtl.ir._
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import firrtl.options.{Dependency, InputAnnotationFileAnnotation, StageMain}
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import firrtl.passes.memlib.ReplSeqMemAnnotation
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import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage, OutputFileAnnotation, RunFirrtlTransformAnnotation}
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import firrtl.passes.{ConvertFixedToSInt}
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import firrtl.transforms.BlackBoxResourceFileNameAnno
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import logger.LazyLogging
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// Requires two phases, one to collect modules below synTop in the hierarchy
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// and a second to remove those modules to generate the test harness
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private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
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val outFir: Option[String] = annotations.collectFirst { case OutFirAnnotation(s) => s }
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val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
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// Dump firrtl and annotation files
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@@ -21,11 +21,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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circuit: Circuit,
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annotations: AnnotationSeq,
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): Unit = {
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outFir.foreach { firPath =>
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val outputFile = new java.io.PrintWriter(firPath)
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outputFile.write(circuit.serialize)
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outputFile.close()
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}
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outAnno.foreach { annoPath =>
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val outputFile = new java.io.PrintWriter(annoPath)
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outputFile.write(JsonProtocol.serialize(annotations.filter(_ match {
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@@ -34,16 +29,19 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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case _: EmittedAnnotation[_] => false
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case _: FirrtlCircuitAnnotation => false
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case _: OutAnnoAnnotation => false
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case _: OutFirAnnotation => false
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case _ => true
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})))
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outputFile.close()
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}
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}
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// TODO: Filter out blackbox dumping from this FIRRTL step, let CIRCT do it
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// Top Generation
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def executeTop(): Unit = {
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val annos = new FirrtlStage().execute(Array.empty, annotations)
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val annos = new FirrtlStage().execute(Array.empty, annotations) //++ Seq(
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// RunFirrtlTransformAnnotation(Dependency[CheckForUnsupportedFirtoolTypes]
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//)))
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annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
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case Some(circuit) =>
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dump(circuit, annos)
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@@ -14,19 +14,6 @@ sealed trait TapeoutOption extends Unserializable {
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this: Annotation =>
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}
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case class OutFirAnnotation(outFir: String) extends NoTargetAnnotation with TapeoutOption
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object OutFirAnnotation extends HasShellOptions {
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val options: Seq[ShellOption[_]] = Seq(
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new ShellOption[String](
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longOption = "out-fir-file",
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shortOption = Some("off"),
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toAnnotationSeq = (s: String) => Seq(OutFirAnnotation(s)),
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helpText = "out-fir-file"
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)
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)
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}
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case class OutAnnoAnnotation(outAnno: String) extends NoTargetAnnotation with TapeoutOption
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object OutAnnoAnnotation extends HasShellOptions {
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@@ -46,7 +33,6 @@ trait TapeoutCli {
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Seq(
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OutAnnoAnnotation,
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OutFirAnnotation,
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).foreach(_.addOptions(parser))
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}
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