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Fix typos

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This commit is contained in:
Edward Wang
2017-07-21 10:33:19 -07:00
committed by edwardcwang
parent 80ca2e538f
commit cf0d40f658
1 changed files with 4 additions and 4 deletions
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8
tapeout/src/main/scala/transforms/macros/Utils.scala
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@@ -25,13 +25,13 @@ class FirrtlMacroPort(port: MacroPort) {
// Bundle representing this macro port. // Bundle representing this macro port.
val tpe = BundleType(Seq( val tpe = BundleType(Seq(
Field(port.clock.name, Flip, ClockType), Field(port.clock.name, Flip, ClockType),
Field(port.address.name, Flip, AddrType)) ++ Field(port.address.name, Flip, addrType)) ++
(port.input map (p => Field(p.name, Flip, DataType))) ++ (port.input map (p => Field(p.name, Flip, dataType))) ++
(port.output map (p => Field(p.name, Default, DataType))) ++ (port.output map (p => Field(p.name, Default, dataType))) ++
(port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++ (port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++
(port.readEnable map (p => Field(p.name, Flip, BoolType))) ++ (port.readEnable map (p => Field(p.name, Flip, BoolType))) ++
(port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++ (port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++
(port.maskPort map (p => Field(p.name, Flip, MaskType))) (port.maskPort map (p => Field(p.name, Flip, maskType)))
) )
val ports = tpe.fields map (f => Port( val ports = tpe.fields map (f => Port(
NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe)) NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))