From cf0d40f658ba4d14d286655ed294306518f2334e Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Fri, 21 Jul 2017 10:33:19 -0700 Subject: [PATCH] Fix typos --- tapeout/src/main/scala/transforms/macros/Utils.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tapeout/src/main/scala/transforms/macros/Utils.scala b/tapeout/src/main/scala/transforms/macros/Utils.scala index 49c6d07f..275943e8 100644 --- a/tapeout/src/main/scala/transforms/macros/Utils.scala +++ b/tapeout/src/main/scala/transforms/macros/Utils.scala @@ -25,13 +25,13 @@ class FirrtlMacroPort(port: MacroPort) { // Bundle representing this macro port. val tpe = BundleType(Seq( Field(port.clock.name, Flip, ClockType), - Field(port.address.name, Flip, AddrType)) ++ - (port.input map (p => Field(p.name, Flip, DataType))) ++ - (port.output map (p => Field(p.name, Default, DataType))) ++ + Field(port.address.name, Flip, addrType)) ++ + (port.input map (p => Field(p.name, Flip, dataType))) ++ + (port.output map (p => Field(p.name, Default, dataType))) ++ (port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++ (port.readEnable map (p => Field(p.name, Flip, BoolType))) ++ (port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++ - (port.maskPort map (p => Field(p.name, Flip, MaskType))) + (port.maskPort map (p => Field(p.name, Flip, maskType))) ) val ports = tpe.fields map (f => Port( NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))